[llvm] r245741 - [PowerPC] PPCVSXFMAMutate should not segfault on undef input registers

[Hans Wennborg via llvm-commits]

+Tom for 3.7.1

On Wed, Aug 26, 2015 at 4:19 PM, Hans Wennborg <hans at chromium.org> wrote:
> Hi Hal,
>
> While there will be an rc4, I would rather not merge this as it's late
> in the process and I want to keep the number of merges to a minimum.
> It will be an excellent patch to get for 3.7.1.
>
> Thanks,
> Hans
>
> On Fri, Aug 21, 2015 at 4:58 PM, Hans Wennborg <hans at chromium.org> wrote:
>> I've put it on my patch list in case we do another release candidate
>> (which seems fairly likely at this point).
>>
>> Thanks,
>> Hans
>>
>> On Fri, Aug 21, 2015 at 4:25 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>>> Hi Hans,
>>>
>>> This should be safe for the release branch.
>>>
>>>  -Hal
>>>
>>> ----- Original Message -----
>>>> From: "Hal Finkel via llvm-commits" <llvm-commits at lists.llvm.org>
>>>> To: llvm-commits at lists.llvm.org
>>>> Sent: Friday, August 21, 2015 4:34:25 PM
>>>> Subject: [llvm] r245741 - [PowerPC] PPCVSXFMAMutate should not segfault on undef input registers
>>>>
>>>> Author: hfinkel
>>>> Date: Fri Aug 21 16:34:24 2015
>>>> New Revision: 245741
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=245741&view=rev
>>>> Log:
>>>> [PowerPC] PPCVSXFMAMutate should not segfault on undef input
>>>> registers
>>>>
>>>> When PPCVSXFMAMutate would look at the input addend register, it
>>>> would get its
>>>> input value number. This would fail, however, if the register was
>>>> undef,
>>>> causing a segfault. Don't segfault (just skip such FMA instructions).
>>>>
>>>> Fixes the test case from PR24542 (although that may have been
>>>> over-reduced).
>>>>
>>>> Added:
>>>>     llvm/trunk/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
>>>> Modified:
>>>>     llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
>>>>
>>>> Modified: llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp?rev=245741&r1=245740&r2=245741&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp (original)
>>>> +++ llvm/trunk/lib/Target/PowerPC/PPCVSXFMAMutate.cpp Fri Aug 21
>>>> 16:34:24 2015
>>>> @@ -103,6 +103,11 @@ protected:
>>>>
>>>>          VNInfo *AddendValNo =
>>>>            LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn();
>>>> +        if (!AddendValNo) {
>>>> +          // This can be null if the register is undef.
>>>> +          continue;
>>>> +        }
>>>> +
>>>>          MachineInstr *AddendMI =
>>>>          LIS->getInstructionFromIndex(AddendValNo->def);
>>>>
>>>>          // The addend and this instruction must be in the same
>>>>          block.
>>>>
>>>> Added: llvm/trunk/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll?rev=245741&view=auto
>>>> ==============================================================================
>>>> --- llvm/trunk/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll (added)
>>>> +++ llvm/trunk/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll Fri Aug
>>>> 21 16:34:24 2015
>>>> @@ -0,0 +1,33 @@
>>>> +; RUN: llc < %s | FileCheck %s
>>>> +target datalayout = "e-m:e-i64:64-n32:64"
>>>> +target triple = "powerpc64le-unknown-linux-gnu"
>>>> +
>>>> +; Function Attrs: nounwind
>>>> +define void @acosh_float8() #0 {
>>>> +entry:
>>>> +  br i1 undef, label %if.then, label %if.end
>>>> +
>>>> +if.then:                                          ; preds = %entry
>>>> +  %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef,
>>>> <4 x float> <float 0x3FE62E4200000000, float 0x3FE62E4200000000,
>>>> float 0x3FE62E4200000000, float 0x3FE62E4200000000>, <4 x float>
>>>> undef) #0
>>>> +  %astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32>
>>>> +  %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, undef
>>>> +  %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, undef
>>>> +  %astype5.i.i.80.i = bitcast <4 x i32> %or.i.i.79.i to <4 x float>
>>>> +  %1 = shufflevector <4 x float> %astype5.i.i.80.i, <4 x float>
>>>> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef,
>>>> i32 undef, i32 undef>
>>>> +  %2 = shufflevector <8 x float> undef, <8 x float> %1, <8 x i32>
>>>> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
>>>> +  store <8 x float> %2, <8 x float>* undef, align 32
>>>> +  br label %if.end
>>>> +
>>>> +; CHECK-LABEL: @acosh_float8
>>>> +; CHECK: xvmaddasp
>>>> +
>>>> +if.end:                                           ; preds =
>>>> %if.then, %entry
>>>> +  ret void
>>>> +}
>>>> +
>>>> +; Function Attrs: nounwind readnone
>>>> +declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4
>>>> x float>) #1
>>>> +
>>>> +attributes #0 = { nounwind }
>>>> +attributes #1 = { nounwind readnone }
>>>> +
>>>>
>>>>
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>>>>
>>>
>>> --
>>> Hal Finkel
>>> Assistant Computational Scientist
>>> Leadership Computing Facility
>>> Argonne National Laboratory