[PATCH] D12724: [CostModel][AArch64] Remove amortization factor for some of the vector select instructions

[Arnold via llvm-commits]

LGTM assuming we don't pessimize those instructions anymore.

Did you run the test suite?

> On Sep 9, 2015, at 4:48 AM, James Molloy <james at jamesmolloy.co.uk> wrote:
> 
> Hi Silviu,
> 
> I agree that we're no longer pessimizing select patterns on ARM or AArch64 with oversize vectors (although I haven't checked i64's, so I'll take your advice there), so this LGTM.
> 
> But please wait for any objections from Nadav/Arnold/Gerolf as it was Nadav and Arnold who added this change in the first place (copied from ARM).
> 
> James
> 
>> On Wed, 9 Sep 2015 at 12:44 silviu.baranga at arm.com via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>> sbaranga created this revision.
>> sbaranga added a subscriber: llvm-commits.
>> Herald added subscribers: rengolin, aemerson.
>> 
>> We are not scalarizing the wide selects in codegen for i16 and i32 and
>> therefore we can remove the amortization factor. We still have issues
>> with i64 vectors in codegen though.
>> 
>> http://reviews.llvm.org/D12724
>> 
>> Files:
>>   lib/Target/AArch64/AArch64TargetTransformInfo.cpp
>>   test/Analysis/CostModel/AArch64/select.ll
>> 
>> Index: lib/Target/AArch64/AArch64TargetTransformInfo.cpp
>> ===================================================================
>> --- lib/Target/AArch64/AArch64TargetTransformInfo.cpp
>> +++ lib/Target/AArch64/AArch64TargetTransformInfo.cpp
>> @@ -380,15 +380,16 @@
>>                                         Type *CondTy) {
>> 
>>    int ISD = TLI->InstructionOpcodeToISD(Opcode);
>> -  // We don't lower vector selects well that are wider than the register width.
>> +  // We don't lower some vector selects well that are wider than the register
>> +  // width.
>>    if (ValTy->isVectorTy() && ISD == ISD::SELECT) {
>>      // We would need this many instructions to hide the scalarization happening.
>>      const int AmortizationCost = 20;
>>      static const TypeConversionCostTblEntry<MVT::SimpleValueType>
>>      VectorSelectTbl[] = {
>> -      { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 * AmortizationCost },
>> -      { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 * AmortizationCost },
>> -      { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 * AmortizationCost },
>> +      { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 },
>> +      { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
>> +      { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 },
>>        { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
>>        { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
>>        { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
>> Index: test/Analysis/CostModel/AArch64/select.ll
>> ===================================================================
>> --- test/Analysis/CostModel/AArch64/select.ll
>> +++ test/Analysis/CostModel/AArch64/select.ll
>> @@ -17,22 +17,22 @@
>>    ; CHECK: cost of 1 {{.*}} select
>>    %v6 = select i1 undef, double undef, double undef
>> 
>> -  ; Vector values - check for vectors that have a high cost because they end up
>> -  ; scalarized.
>> -  ; CHECK: cost of 320 {{.*}} select
>> +  ; CHECK: cost of 16 {{.*}} select
>>    %v13b = select <16 x i1>  undef, <16 x i16> undef, <16 x i16> undef
>> 
>> -  ; CHECK: cost of 160 {{.*}} select
>> +  ; CHECK: cost of 8 {{.*}} select
>>    %v15b = select <8 x i1>  undef, <8 x i32> undef, <8 x i32> undef
>> -  ; CHECK: cost of 320 {{.*}} select
>> +  ; CHECK: cost of 16 {{.*}} select
>>    %v15c = select <16 x i1>  undef, <16 x i32> undef, <16 x i32> undef
>> 
>> +  ; Vector values - check for vectors of i64s that have a high cost because
>> +  ; they end up scalarized.
>>    ; CHECK: cost of 80 {{.*}} select
>>    %v16a = select <4 x i1> undef, <4 x i64> undef, <4 x i64> undef
>>    ; CHECK: cost of 160 {{.*}} select
>>    %v16b = select <8 x i1> undef, <8 x i64> undef, <8 x i64> undef
>>    ; CHECK: cost of 320 {{.*}} select
>>    %v16c = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef
>> 
>> -    ret void
>> +  ret void
>>  }
>> 
>> 
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