[PATCH] D12591: Fix vector splitting for extract_vector_elt and vector elements of <8-bits.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 9 02:54:37 PDT 2015
This revision was automatically updated to reflect the committed changes.
Closed by commit rL247128: Fix vector splitting for extract_vector_elt and vector elements of <8-bits. (authored by dsanders).
Changed prior to commit:
http://reviews.llvm.org/D12591?vs=33914&id=34304#toc
Repository:
rL LLVM
http://reviews.llvm.org/D12591
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/test/CodeGen/Mips/llvm-ir/extractelement.ll
Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/extractelement.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/extractelement.ll
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/extractelement.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
+
+; This test triggered a bug in the vector splitting where the type legalizer
+; attempted to extract the element with by storing the vector, then reading
+; an element back. However, the address calculation was:
+; Base + Index * (EltSizeInBits / 8)
+; and EltSizeInBits was 1. This caused the index to be forgotten.
+define i1 @via_stack_bug(i8 signext %idx) {
+ %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx
+ ret i1 %1
+}
+
+; ALL-LABEL: via_stack_bug:
+; ALL-DAG: addiu [[ONE:\$[0-9]+]], $zero, 1
+; ALL-DAG: sb [[ONE]], 7($sp)
+; ALL-DAG: sb $zero, 6($sp)
+; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6
+; ALL-DAG: addu [[EPTR:\$[0-9]+]], $4, [[VPTR]]
+; ALL: lbu $2, 0([[EPTR]])
Index: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1554,9 +1554,25 @@
if (CustomLowerNode(N, N->getValueType(0), true))
return SDValue();
- // Store the vector to the stack.
- EVT EltVT = VecVT.getVectorElementType();
+ // Make the vector elements byte-addressable if they aren't already.
SDLoc dl(N);
+ EVT EltVT = VecVT.getVectorElementType();
+ if (EltVT.getSizeInBits() < 8) {
+ SmallVector<SDValue, 4> ElementOps;
+ for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
+ ElementOps.push_back(DAG.getAnyExtOrTrunc(
+ DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
+ DAG.getConstant(i, dl, MVT::i8)),
+ dl, MVT::i8));
+ }
+
+ EltVT = MVT::i8;
+ VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
+ VecVT.getVectorNumElements());
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
+ }
+
+ // Store the vector to the stack.
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
MachinePointerInfo(), false, false, 0);
Index: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -1007,6 +1007,8 @@
// Calculate the element offset and add it to the pointer.
unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size.
+ assert(EltSize * 8 == EltVT.getSizeInBits() &&
+ "Converting bits to bytes lost precision");
Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
DAG.getConstant(EltSize, dl, Index.getValueType()));
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