[llvm] r247065 - [WebAssembly] Support running without a register allocator in the default CodeGen passes

[Dan Gohman via llvm-commits]

Author: djg
Date: Tue Sep  8 15:36:33 2015
New Revision: 247065

URL: http://llvm.org/viewvc/llvm-project?rev=247065&view=rev
Log:
[WebAssembly] Support running without a register allocator in the default CodeGen passes

This allows backends which don't use a traditional register allocator,
but do need PHI lowering and other passes, to use the default
TargetPassConfig::addFastRegAlloc and
TargetPassConfig::addOptimizedRegAlloc implementations.

Differential Revision: http://reviews.llvm.org/D12691

Modified:
    llvm/trunk/lib/CodeGen/Passes.cpp
    llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

Modified: llvm/trunk/lib/CodeGen/Passes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=247065&r1=247064&r2=247065&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Passes.cpp (original)
+++ llvm/trunk/lib/CodeGen/Passes.cpp Tue Sep  8 15:36:33 2015
@@ -704,7 +704,8 @@ void TargetPassConfig::addFastRegAlloc(F
   addPass(&PHIEliminationID, false);
   addPass(&TwoAddressInstructionPassID, false);
 
-  addPass(RegAllocPass);
+  if (RegAllocPass)
+    addPass(RegAllocPass);
 }
 
 /// Add standard target-independent passes that are tightly coupled with
@@ -735,25 +736,27 @@ void TargetPassConfig::addOptimizedRegAl
   // PreRA instruction scheduling.
   addPass(&MachineSchedulerID);
 
-  // Add the selected register allocation pass.
-  addPass(RegAllocPass);
-
-  // Allow targets to change the register assignments before rewriting.
-  addPreRewrite();
-
-  // Finally rewrite virtual registers.
-  addPass(&VirtRegRewriterID);
-
-  // Perform stack slot coloring and post-ra machine LICM.
-  //
-  // FIXME: Re-enable coloring with register when it's capable of adding
-  // kill markers.
-  addPass(&StackSlotColoringID);
-
-  // Run post-ra machine LICM to hoist reloads / remats.
-  //
-  // FIXME: can this move into MachineLateOptimization?
-  addPass(&PostRAMachineLICMID);
+  if (RegAllocPass) {
+    // Add the selected register allocation pass.
+    addPass(RegAllocPass);
+
+    // Allow targets to change the register assignments before rewriting.
+    addPreRewrite();
+
+    // Finally rewrite virtual registers.
+    addPass(&VirtRegRewriterID);
+
+    // Perform stack slot coloring and post-ra machine LICM.
+    //
+    // FIXME: Re-enable coloring with register when it's capable of adding
+    // kill markers.
+    addPass(&StackSlotColoringID);
+
+    // Run post-ra machine LICM to hoist reloads / remats.
+    //
+    // FIXME: can this move into MachineLateOptimization?
+    addPass(&PostRAMachineLICMID);
+  }
 }
 
 //===---------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp?rev=247065&r1=247064&r2=247065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp Tue Sep  8 15:36:33 2015
@@ -94,15 +94,12 @@ public:
   }
 
   FunctionPass *createTargetRegisterAllocator(bool) override;
-  void addFastRegAlloc(FunctionPass *RegAllocPass) override;
-  void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
 
   void addIRPasses() override;
   bool addPreISel() override;
   bool addInstSelector() override;
   bool addILPOpts() override;
   void addPreRegAlloc() override;
-  void addRegAllocPasses(bool Optimized);
   void addPostRegAlloc() override;
   void addPreSched2() override;
   void addPreEmitPass() override;
@@ -124,16 +121,6 @@ FunctionPass *WebAssemblyPassConfig::cre
   return nullptr; // No reg alloc
 }
 
-void WebAssemblyPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
-  assert(!RegAllocPass && "WebAssembly uses no regalloc!");
-  addRegAllocPasses(false);
-}
-
-void WebAssemblyPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
-  assert(!RegAllocPass && "WebAssembly uses no regalloc!");
-  addRegAllocPasses(true);
-}
-
 //===----------------------------------------------------------------------===//
 // The following functions are called from lib/CodeGen/Passes.cpp to modify
 // the CodeGen pass sequence.
@@ -164,28 +151,6 @@ bool WebAssemblyPassConfig::addILPOpts()
 
 void WebAssemblyPassConfig::addPreRegAlloc() {}
 
-void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {
-  // This is list is derived from the regalloc pass list used in
-  // addFastRegAlloc and addOptimizedRegAlloc in lib/CodeGen/Passes.cpp. We
-  // don't run the actual register allocator, but we do run the passes which
-  // lower SSA form, so after these passes are complete, we have non-SSA
-  // virtual registers.
-
-  if (Optimized) {
-    addPass(&ProcessImplicitDefsID);
-    addPass(&LiveVariablesID);
-    addPass(&MachineLoopInfoID);
-  }
-
-  addPass(&PHIEliminationID);
-  addPass(&TwoAddressInstructionPassID, false);
-
-  if (Optimized) {
-    addPass(&RegisterCoalescerID);
-    addPass(&MachineSchedulerID);
-  }
-}
-
 void WebAssemblyPassConfig::addPostRegAlloc() {
   // FIXME: the following passes dislike virtual registers. Disable them for now
   //        so that basic tests can pass. Future patches will remedy this.