[llvm] r246960 - [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions
Zoran Jovanovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 7 03:31:31 PDT 2015
Author: zjovanovic
Date: Mon Sep 7 05:31:31 2015
New Revision: 246960
URL: http://llvm.org/viewvc/llvm-project?rev=246960&view=rev
Log:
[mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions
Differential Revision: http://reviews.llvm.org/D12141
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
llvm/trunk/test/MC/Mips/micromips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Mon Sep 7 05:31:31 2015
@@ -365,3 +365,65 @@ class POOL32F_MOV_NEG_FM_MMR6<string ins
let Inst{12-6} = funct;
let Inst{5-0} = 0b111011;
}
+
+class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> ft;
+ bits<5> fs;
+ bits<5> fd;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b010101;
+ let Inst{25-21} = ft;
+ let Inst{20-16} = fs;
+ let Inst{15-11} = fd;
+ let Inst{10-9} = fmt;
+ let Inst{8-0} = funct;
+}
+
+class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> ft;
+ bits<5> fs;
+ bits<5> fd;
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b010101;
+ let Inst{25-21} = ft;
+ let Inst{20-16} = fs;
+ let Inst{15-11} = fd;
+ let Inst{10-6} = Cond.Value;
+ let Inst{5-0} = format;
+}
+
+class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> ft;
+ bits<5> fs;
+
+ bits<32> Inst;
+ let Inst{31-26} = 0b010101;
+ let Inst{25-21} = ft;
+ let Inst{20-16} = fs;
+ let Inst{15} = 0;
+ let Inst{14} = fmt;
+ let Inst{13-6} = funct;
+ let Inst{5-0} = 0b111011;
+}
+
+class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
+ bits<5> ft;
+ bits<5> fs;
+
+ bits<32> Inst;
+ let Inst{31-26} = 0b010101;
+ let Inst{25-21} = ft;
+ let Inst{20-16} = fs;
+ let Inst{15} = 0;
+ let Inst{14-13} = fmt;
+ let Inst{12-6} = funct;
+ let Inst{5-0} = 0b111011;
+}
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Mon Sep 7 05:31:31 2015
@@ -127,6 +127,25 @@ class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_
class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
+class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
+class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
+class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
+class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
+class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
+class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
+class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
+class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
+
+class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
+class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
+class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
+class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
+class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
+class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
+class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
+class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
+class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
+class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
//===----------------------------------------------------------------------===//
//
@@ -381,6 +400,117 @@ class FNEG_S_MMR6_DESC
class FNEG_D_MMR6_DESC
: FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
+class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
+class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
+class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
+class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
+
+class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
+class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
+class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
+class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
+
+class CVT_MMR6_DESC_BASE<
+ string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
+ InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
+ : HARDFLOAT, NeverHasSideEffects {
+ dag OutOperandList = (outs DstRC:$ft);
+ dag InOperandList = (ins SrcRC:$fs);
+ string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
+ list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
+ InstrItinClass Itinerary = Itin;
+ Format Form = FrmFR;
+}
+
+class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
+ II_CVT>;
+class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
+ II_CVT>;
+class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
+ II_CVT>;
+class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
+ II_CVT>;
+class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
+ II_CVT>;
+class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
+ II_CVT>;
+class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
+ II_CVT>, FGR_64;
+class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
+ II_CVT>;
+class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
+ II_CVT>;
+class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
+ II_CVT>, FGR_64;
+
+multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
+ RegisterOperand FGROpnd> {
+ def CMP_AF_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_UN_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
+ CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_EQ_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
+ CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_UEQ_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
+ CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_LT_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_ULT_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
+ CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_LE_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_ULE_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
+ CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SAF_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SUN_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SEQ_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
+ CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SLT_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SULT_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SLE_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+ def CMP_SULE_#NAME : POOL32F_CMP_FM<
+ !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
+ ISA_MICROMIPS32R6;
+}
+
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@@ -491,6 +621,40 @@ def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR
ISA_MICROMIPS32R6;
def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
ISA_MICROMIPS32R6;
+def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
+def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
+def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
+def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
+def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
+ ISA_MICROMIPS32R6;
+defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
+defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Mon Sep 7 05:31:31 2015
@@ -186,54 +186,56 @@ class CMP_CONDN_DESC_BASE<string CondStr
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
RegisterOperand FGROpnd>{
- def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
- CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
- CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
- CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
- CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
+ let AdditionalPredicates = [NotInMicroMips] in {
+ def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
- CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
- CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
- CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
- CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,
- CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,
- CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
- CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,
- CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
+ def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
+ CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,
- CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,
- CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
+ def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
+ CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
ISA_MIPS32R6, HARDFLOAT;
- def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,
- CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
- ISA_MIPS32R6, HARDFLOAT;
- def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,
- CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
+ def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
+ CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
+ CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,
ISA_MIPS32R6, HARDFLOAT;
+ def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
+ CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
+ CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
+ ISA_MIPS32R6, HARDFLOAT;
+ }
}
//===----------------------------------------------------------------------===//
@@ -705,15 +707,15 @@ def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_M
let AdditionalPredicates = [NotInMicroMips] in {
def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
}
-def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
-def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Mon Sep 7 05:31:31 2015
@@ -305,10 +305,12 @@ let DecoderNamespace = "Mips64" in {
def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x20, 20>;
-def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
- ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
-def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
- ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
+let AdditionalPredicates = [NotInMicroMips] in{
+ def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
+ ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
+ def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
+ ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
+}
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_32;
@@ -320,8 +322,10 @@ def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s"
let DecoderNamespace = "Mips64" in {
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>, FGR_64;
- def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
- ABSS_FM<0x20, 21>, FGR_64;
+ let AdditionalPredicates = [NotInMicroMips] in{
+ def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
+ ABSS_FM<0x20, 21>, FGR_64;
+ }
def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
ABSS_FM<0x21, 20>, FGR_64;
def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt Mon Sep 7 05:31:31 2015
@@ -165,3 +165,103 @@
0x54,0xc7,0x0b,0x7b # CHECK: neg.s $f6, $f7
0x54,0x86,0x2b,0x7b # CHECK: neg.d $f4, $f6
+
+0x54 0x64 0x28 0x0b # CHECK: max.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x0b # CHECK: max.d $f5, $f4, $f3
+
+0x54 0x64 0x28 0x2b # CHECK: maxa.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x2b # CHECK: maxa.d $f5, $f4, $f3
+
+0x54 0x64 0x28 0x03 # CHECK: min.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x03 # CHECK: min.d $f5, $f4, $f3
+
+0x54 0x64 0x28 0x23 # CHECK: mina.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x23 # CHECK: mina.d $f5, $f4, $f3
+
+0x54 0x83 0x10 0x05 # CHECK: cmp.af.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0x45 # CHECK: cmp.un.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0x85 # CHECK: cmp.eq.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0xc5 # CHECK: cmp.ueq.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0x05 # CHECK: cmp.lt.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0x45 # CHECK: cmp.ult.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0x85 # CHECK: cmp.le.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0xc5 # CHECK: cmp.ule.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0x05 # CHECK: cmp.saf.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0x45 # CHECK: cmp.sun.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0x85 # CHECK: cmp.seq.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0xc5 # CHECK: cmp.sueq.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0x05 # CHECK: cmp.slt.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0x45 # CHECK: cmp.sult.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0x85 # CHECK: cmp.sle.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0xc5 # CHECK: cmp.sule.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0x15 # CHECK: cmp.af.d $f2, $f3, $f4
+
+0x54 0x83 0x10 0x55 # CHECK: cmp.un.d $f2, $f3, $f4
+
+0x54 0x83 0x10 0x95 # CHECK: cmp.eq.d $f2, $f3, $f4
+
+0x54 0x83 0x10 0xd5 # CHECK: cmp.ueq.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0x15 # CHECK: cmp.lt.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0x55 # CHECK: cmp.ult.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0x95 # CHECK: cmp.le.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0xd5 # CHECK: cmp.ule.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0x15 # CHECK: cmp.saf.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0x55 # CHECK: cmp.sun.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0x95 # CHECK: cmp.seq.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0xd5 # CHECK: cmp.sueq.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0x15 # CHECK: cmp.slt.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0x55 # CHECK: cmp.sult.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0x95 # CHECK: cmp.sle.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0xd5 # CHECK: cmp.sule.d $f2, $f3, $f4
+
+0x54 0x64 0x01 0x3b # CHECK: cvt.l.s $f3, $f4
+
+0x54 0x64 0x41 0x3b # CHECK: cvt.l.d $f3, $f4
+
+0x54 0x64 0x09 0x3b # CHECK: cvt.w.s $f3, $f4
+
+0x54 0x64 0x49 0x3b # CHECK: cvt.w.d $f3, $f4
+
+0x54 0x44 0x13 0x7b # CHECK: cvt.d.s $f2, $f4
+
+0x54 0x44 0x33 0x7b # CHECK: cvt.d.w $f2, $f4
+
+0x54 0x44 0x53 0x7b # CHECK: cvt.d.l $f2, $f4
+
+0x54,0x44,0x1b,0x7b # CHECK: cvt.s.d $f2, $f4
+
+0x54,0x64,0x3b,0x7b # CHECK: cvt.s.w $f3, $f4
+
+0x54,0x64,0x5b,0x7b # CHECK: cvt.s.l $f3, $f4
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt Mon Sep 7 05:31:31 2015
@@ -71,3 +71,103 @@
0x54,0xc7,0x0b,0x7b # CHECK: neg.s $f6, $f7
0x54,0x86,0x2b,0x7b # CHECK: neg.d $f4, $f6
+
+0x54 0x64 0x28 0x0b # CHECK: max.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x0b # CHECK: max.d $f5, $f4, $f3
+
+0x54 0x64 0x28 0x2b # CHECK: maxa.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x2b # CHECK: maxa.d $f5, $f4, $f3
+
+0x54 0x64 0x28 0x03 # CHECK: min.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x03 # CHECK: min.d $f5, $f4, $f3
+
+0x54 0x64 0x28 0x23 # CHECK: mina.s $f5, $f4, $f3
+
+0x54 0x64 0x2a 0x23 # CHECK: mina.d $f5, $f4, $f3
+
+0x54 0x83 0x10 0x05 # CHECK: cmp.af.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0x45 # CHECK: cmp.un.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0x85 # CHECK: cmp.eq.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0xc5 # CHECK: cmp.ueq.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0x05 # CHECK: cmp.lt.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0x45 # CHECK: cmp.ult.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0x85 # CHECK: cmp.le.s $f2, $f3, $f4
+
+0x54 0x83 0x11 0xc5 # CHECK: cmp.ule.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0x05 # CHECK: cmp.saf.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0x45 # CHECK: cmp.sun.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0x85 # CHECK: cmp.seq.s $f2, $f3, $f4
+
+0x54 0x83 0x12 0xc5 # CHECK: cmp.sueq.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0x05 # CHECK: cmp.slt.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0x45 # CHECK: cmp.sult.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0x85 # CHECK: cmp.sle.s $f2, $f3, $f4
+
+0x54 0x83 0x13 0xc5 # CHECK: cmp.sule.s $f2, $f3, $f4
+
+0x54 0x83 0x10 0x15 # CHECK: cmp.af.d $f2, $f3, $f4
+
+0x54 0x83 0x10 0x55 # CHECK: cmp.un.d $f2, $f3, $f4
+
+0x54 0x83 0x10 0x95 # CHECK: cmp.eq.d $f2, $f3, $f4
+
+0x54 0x83 0x10 0xd5 # CHECK: cmp.ueq.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0x15 # CHECK: cmp.lt.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0x55 # CHECK: cmp.ult.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0x95 # CHECK: cmp.le.d $f2, $f3, $f4
+
+0x54 0x83 0x11 0xd5 # CHECK: cmp.ule.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0x15 # CHECK: cmp.saf.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0x55 # CHECK: cmp.sun.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0x95 # CHECK: cmp.seq.d $f2, $f3, $f4
+
+0x54 0x83 0x12 0xd5 # CHECK: cmp.sueq.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0x15 # CHECK: cmp.slt.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0x55 # CHECK: cmp.sult.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0x95 # CHECK: cmp.sle.d $f2, $f3, $f4
+
+0x54 0x83 0x13 0xd5 # CHECK: cmp.sule.d $f2, $f3, $f4
+
+0x54 0x64 0x01 0x3b # CHECK: cvt.l.s $f3, $f4
+
+0x54 0x64 0x41 0x3b # CHECK: cvt.l.d $f3, $f4
+
+0x54 0x64 0x09 0x3b # CHECK: cvt.w.s $f3, $f4
+
+0x54 0x64 0x49 0x3b # CHECK: cvt.w.d $f3, $f4
+
+0x54 0x44 0x13 0x7b # CHECK: cvt.d.s $f2, $f4
+
+0x54 0x44 0x33 0x7b # CHECK: cvt.d.w $f2, $f4
+
+0x54 0x44 0x53 0x7b # CHECK: cvt.d.l $f2, $f4
+
+0x54,0x44,0x1b,0x7b # CHECK: cvt.s.d $f2, $f4
+
+0x54,0x64,0x3b,0x7b # CHECK: cvt.s.w $f3, $f4
+
+0x54,0x64,0x5b,0x7b # CHECK: cvt.s.l $f3, $f4
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Mon Sep 7 05:31:31 2015
@@ -85,4 +85,54 @@
mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b]
neg.s $f6, $f7 # CHECK: neg.s $f6, $f7 # encoding: [0x54,0xc7,0x0b,0x7b]
neg.d $f4, $f6 # CHECK: neg.d $f4, $f6 # encoding: [0x54,0x86,0x2b,0x7b]
+ max.s $f5, $f4, $f3 # CHECK: max.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x0b]
+ max.d $f5, $f4, $f3 # CHECK: max.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x0b]
+ maxa.s $f5, $f4, $f3 # CHECK: maxa.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x2b]
+ maxa.d $f5, $f4, $f3 # CHECK: maxa.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x2b]
+ min.s $f5, $f4, $f3 # CHECK: min.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x03]
+ min.d $f5, $f4, $f3 # CHECK: min.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x03]
+ mina.s $f5, $f4, $f3 # CHECK: mina.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x23]
+ mina.d $f5, $f4, $f3 # CHECK: mina.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x23]
+ cmp.af.s $f2, $f3, $f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x05]
+ cmp.af.d $f2, $f3, $f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x15]
+ cmp.un.s $f2, $f3, $f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x45]
+ cmp.un.d $f2, $f3, $f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x55]
+ cmp.eq.s $f2, $f3, $f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x85]
+ cmp.eq.d $f2, $f3, $f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x95]
+ cmp.ueq.s $f2, $f3, $f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0xc5]
+ cmp.ueq.d $f2, $f3, $f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0xd5]
+ cmp.lt.s $f2, $f3, $f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x05]
+ cmp.lt.d $f2, $f3, $f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x15]
+ cmp.ult.s $f2, $f3, $f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x45]
+ cmp.ult.d $f2, $f3, $f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x55]
+ cmp.le.s $f2, $f3, $f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x85]
+ cmp.le.d $f2, $f3, $f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x95]
+ cmp.ule.s $f2, $f3, $f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0xc5]
+ cmp.ule.d $f2, $f3, $f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0xd5]
+ cmp.saf.s $f2, $f3, $f4 # CHECK: cmp.saf.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x05]
+ cmp.saf.d $f2, $f3, $f4 # CHECK: cmp.saf.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x15]
+ cmp.sun.s $f2, $f3, $f4 # CHECK: cmp.sun.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x45]
+ cmp.sun.d $f2, $f3, $f4 # CHECK: cmp.sun.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x55]
+ cmp.seq.s $f2, $f3, $f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x85]
+ cmp.seq.d $f2, $f3, $f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x95]
+ cmp.sueq.s $f2, $f3, $f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0xc5]
+ cmp.sueq.d $f2, $f3, $f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0xd5]
+ cmp.slt.s $f2, $f3, $f4 # CHECK: cmp.slt.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x05]
+ cmp.slt.d $f2, $f3, $f4 # CHECK: cmp.slt.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x15]
+ cmp.sult.s $f2, $f3, $f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x45]
+ cmp.sult.d $f2, $f3, $f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x55]
+ cmp.sle.s $f2, $f3, $f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x85]
+ cmp.sle.d $f2, $f3, $f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x95]
+ cmp.sule.s $f2, $f3, $f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xc5]
+ cmp.sule.d $f2, $f3, $f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xd5]
+ cvt.l.s $f3, $f4 # CHECK: cvt.l.s $f3, $f4 # encoding: [0x54,0x64,0x01,0x3b]
+ cvt.l.d $f3, $f4 # CHECK: cvt.l.d $f3, $f4 # encoding: [0x54,0x64,0x41,0x3b]
+ cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b]
+ cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b]
+ cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b]
+ cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b]
+ cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b]
+ cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b]
+ cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b]
+ cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b]
Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=246960&r1=246959&r2=246960&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Mon Sep 7 05:31:31 2015
@@ -37,5 +37,55 @@ a:
mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b]
neg.s $f6, $f7 # CHECK: neg.s $f6, $f7 # encoding: [0x54,0xc7,0x0b,0x7b]
neg.d $f4, $f6 # CHECK: neg.d $f4, $f6 # encoding: [0x54,0x86,0x2b,0x7b]
+ max.s $f5, $f4, $f3 # CHECK: max.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x0b]
+ max.d $f5, $f4, $f3 # CHECK: max.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x0b]
+ maxa.s $f5, $f4, $f3 # CHECK: maxa.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x2b]
+ maxa.d $f5, $f4, $f3 # CHECK: maxa.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x2b]
+ min.s $f5, $f4, $f3 # CHECK: min.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x03]
+ min.d $f5, $f4, $f3 # CHECK: min.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x03]
+ mina.s $f5, $f4, $f3 # CHECK: mina.s $f5, $f4, $f3 # encoding: [0x54,0x64,0x28,0x23]
+ mina.d $f5, $f4, $f3 # CHECK: mina.d $f5, $f4, $f3 # encoding: [0x54,0x64,0x2a,0x23]
+ cmp.af.s $f2, $f3, $f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x05]
+ cmp.af.d $f2, $f3, $f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x15]
+ cmp.un.s $f2, $f3, $f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x45]
+ cmp.un.d $f2, $f3, $f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x55]
+ cmp.eq.s $f2, $f3, $f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x85]
+ cmp.eq.d $f2, $f3, $f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0x95]
+ cmp.ueq.s $f2, $f3, $f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0xc5]
+ cmp.ueq.d $f2, $f3, $f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x10,0xd5]
+ cmp.lt.s $f2, $f3, $f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x05]
+ cmp.lt.d $f2, $f3, $f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x15]
+ cmp.ult.s $f2, $f3, $f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x45]
+ cmp.ult.d $f2, $f3, $f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x55]
+ cmp.le.s $f2, $f3, $f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x85]
+ cmp.le.d $f2, $f3, $f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0x95]
+ cmp.ule.s $f2, $f3, $f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0xc5]
+ cmp.ule.d $f2, $f3, $f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x11,0xd5]
+ cmp.saf.s $f2, $f3, $f4 # CHECK: cmp.saf.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x05]
+ cmp.saf.d $f2, $f3, $f4 # CHECK: cmp.saf.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x15]
+ cmp.sun.s $f2, $f3, $f4 # CHECK: cmp.sun.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x45]
+ cmp.sun.d $f2, $f3, $f4 # CHECK: cmp.sun.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x55]
+ cmp.seq.s $f2, $f3, $f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x85]
+ cmp.seq.d $f2, $f3, $f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0x95]
+ cmp.sueq.s $f2, $f3, $f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0xc5]
+ cmp.sueq.d $f2, $f3, $f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0xd5]
+ cmp.slt.s $f2, $f3, $f4 # CHECK: cmp.slt.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x05]
+ cmp.slt.d $f2, $f3, $f4 # CHECK: cmp.slt.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x15]
+ cmp.sult.s $f2, $f3, $f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x45]
+ cmp.sult.d $f2, $f3, $f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x55]
+ cmp.sle.s $f2, $f3, $f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x85]
+ cmp.sle.d $f2, $f3, $f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x95]
+ cmp.sule.s $f2, $f3, $f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xc5]
+ cmp.sule.d $f2, $f3, $f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xd5]
+ cvt.l.s $f3, $f4 # CHECK: cvt.l.s $f3, $f4 # encoding: [0x54,0x64,0x01,0x3b]
+ cvt.l.d $f3, $f4 # CHECK: cvt.l.d $f3, $f4 # encoding: [0x54,0x64,0x41,0x3b]
+ cvt.w.s $f3, $f4 # CHECK: cvt.w.s $f3, $f4 # encoding: [0x54,0x64,0x09,0x3b]
+ cvt.w.d $f3, $f4 # CHECK: cvt.w.d $f3, $f4 # encoding: [0x54,0x64,0x49,0x3b]
+ cvt.d.s $f2, $f4 # CHECK: cvt.d.s $f2, $f4 # encoding: [0x54,0x44,0x13,0x7b]
+ cvt.d.w $f2, $f4 # CHECK: cvt.d.w $f2, $f4 # encoding: [0x54,0x44,0x33,0x7b]
+ cvt.d.l $f2, $f4 # CHECK: cvt.d.l $f2, $f4 # encoding: [0x54,0x44,0x53,0x7b]
+ cvt.s.d $f2, $f4 # CHECK: cvt.s.d $f2, $f4 # encoding: [0x54,0x44,0x1b,0x7b]
+ cvt.s.w $f3, $f4 # CHECK: cvt.s.w $f3, $f4 # encoding: [0x54,0x64,0x3b,0x7b]
+ cvt.s.l $f3, $f4 # CHECK: cvt.s.l $f3, $f4 # encoding: [0x54,0x64,0x5b,0x7b]
1:
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