[PATCH] D12656: Change test to allow movzbl, movzwl in place of movb, movw instructions

[Kevin B. Smith via llvm-commits]

kbsmith1 created this revision.
kbsmith1 added reviewers: DavidKreitzer, spatel.
kbsmith1 added a subscriber: llvm-commits.

This change modifies a couple of unit tests to allow movzbl or movzwl instructions to be generated for
byte and word loads, as well as the existing instructions the test allowed (which were movb, movw).
This is first of several test updates to allow this generality/freedom in code generation for X86.

http://reviews.llvm.org/D12656

Files:
  test/CodeGen/X86/half.ll
  test/CodeGen/X86/store-narrow.ll

Index: test/CodeGen/X86/half.ll
===================================================================
--- test/CodeGen/X86/half.ll
+++ test/CodeGen/X86/half.ll
@@ -5,8 +5,8 @@
 
 define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
-; CHECK: movw (%rdi), [[TMP:%[a-z0-9]+]]
-; CHECK: movw [[TMP]], (%rsi)
+; CHECK: {{movw|movzwl}} (%rdi), %{{e?}}[[TMP:[abcd]]]x
+; CHECK: movw %[[TMP]]x, (%rsi)
   %val = load half, half* %in
   store half %val, half* %out
   ret void
Index: test/CodeGen/X86/store-narrow.ll
===================================================================
--- test/CodeGen/X86/store-narrow.ll
+++ test/CodeGen/X86/store-narrow.ll
@@ -17,7 +17,7 @@
 ; X64: movb	%sil, (%rdi)
 
 ; X32-LABEL: test1:
-; X32: movb	8(%esp), %al
+; X32: {{movb|movzbl}}	8(%esp), {{%al|%eax}}
 ; X32: movb	%al, (%{{.*}})
 }
 
@@ -34,7 +34,7 @@
 ; X64: movb	%sil, 1(%rdi)
 
 ; X32-LABEL: test2:
-; X32: movb	8(%esp), %[[REG:[abcd]]]l
+; X32: {{movb|movzbl}}	8(%esp), %{{e?}}[[REG:[abcd]]]{{x|l}}
 ; X32: movb	%[[REG]]l, 1(%{{.*}})
 }
 
@@ -50,7 +50,7 @@
 ; X64: movw	%si, (%rdi)
 
 ; X32-LABEL: test3:
-; X32: movw	8(%esp), %ax
+; X32: {{movw|movzwl}}	8(%esp), {{%ax|%eax}}
 ; X32: movw	%ax, (%{{.*}})
 }
 
@@ -67,7 +67,7 @@
 ; X64: movw	%si, 2(%rdi)
 
 ; X32-LABEL: test4:
-; X32: movw	8(%esp), %[[REG:[abcd]]]x
+; X32: {{movw|movzwl}}	8(%esp), %{{e?}}[[REG:[abcd]]]x
 ; X32: movw	%[[REG]]x, 2(%{{.*}})
 }
 
@@ -84,7 +84,7 @@
 ; X64: movw	%si, 2(%rdi)
 
 ; X32-LABEL: test5:
-; X32: movw	8(%esp), %[[REG:[abcd]]]x
+; X32: {{movw|movzwl}}	8(%esp), %{{e?}}[[REG:[abcd]]]x
 ; X32: movw	%[[REG]]x, 2(%{{.*}})
 }
 
@@ -102,8 +102,8 @@
 
 
 ; X32-LABEL: test6:
-; X32: movb	8(%esp), %[[REG:[abcd]l]]
-; X32: movb	%[[REG]], 5(%{{.*}})
+; X32: {{movb|movzbl}}	8(%esp), %{{e?}}[[REG:[abcd]]]{{x|l}}
+; X32: movb	%[[REG]]l, 5(%{{.*}})
 }
 
 define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind {
@@ -121,8 +121,8 @@
 
 
 ; X32-LABEL: test7:
-; X32: movb	8(%esp), %[[REG:[abcd]l]]
-; X32: movb	%[[REG]], 5(%{{.*}})
+; X32: {{movb|movzbl}}	8(%esp), %{{e?}}[[REG:[abcd]]]{{x|l}}
+; X32: movb	%[[REG]]l, 5(%{{.*}})
 }
 
 ; PR7833


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