[PATCH] D12116: [AArch64] Improve load/store optimizer to handle LDUR + LDR.

[Chad Rosier via llvm-commits]

mcrosier added a comment.

Thanks for the feedback, Ahmed.

In http://reviews.llvm.org/D12116#236954, @ab wrote:

> This LGTM (modulo nits), but let's see what the testsuite says first.


Unfortunately, I don't have a setup that can test with the testsuite at the moment.  That is in the works...

This transformation is very narrow and did not hit anything in Spec2000.  Therefore, I'm going to move onto other work with a higher ROI.  However, feel free to push this one along.

> In http://reviews.llvm.org/D12116#231366, @mzolotukhin wrote:

> 

> > As far as I understand, currently ISelLowering splits the unaligned stores, from which we happen to get STUR and STR, which we can't combine to STP without this patch. With this patch, we'll be able to merge them back, so we'll undo that optimization.

> 

> 

> But this issue isn't specific to this patch, right? If the unaligned store was split to STR+STR we would have generated an STP even before this change.  I agree we'll need to do something about this though, but separately, and for both mixed and non-mixed STR/STUR pairs.


That is absolutely correct!  This patch only applies to the very narrow case of STR/STUR.  The common case is when we're pairing STUR/STUR, which has already been committed.


Repository:
  rL LLVM

http://reviews.llvm.org/D12116