[PATCH] D12479: [X86][AVX512BW] support in byte shift and SAD

[Elena Demikhovsky via llvm-commits]

delena added a comment.

Please apply the comments and you can commit the patch.


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Comment at: ../llvmTmp/lib/Target/X86/X86InstrSSE.td:4187
@@ -4185,3 +4186,3 @@
 
-let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
+let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 , Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
   // 256-bit logical shifts.
----------------
The line is too long.

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Comment at: ../llvmTmp/test/CodeGen/X86/avx512bwvl-intrinsics.ll:4197
@@ -4196,1 +4196,3 @@
 }
+
+define <16 x i16> @shuffle_v16i16_zz_zz_zz_zz_zz_zz_zz_16_zz_zz_zz_zz_zz_zz_zz_24(<16 x i16> %a) {
----------------
This file is for intrinsics. Put in avx-isa-check.ll.


http://reviews.llvm.org/D12479