[PATCH] D12255: AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL246354: AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates (authored by tstellar).

Changed prior to commit:
  http://reviews.llvm.org/D12255?vs=32880&id=33509#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D12255

Files:
  llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp

Index: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -211,8 +211,12 @@
 
     Imm = APInt(64, OpToFold.getImm());
 
+    const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode());
+    const TargetRegisterClass *FoldRC =
+        TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
+
     // Split 64-bit constants into 32-bits for folding.
-    if (UseOp.getSubReg()) {
+    if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
       if (UseRC->getSize() != 8)
         return;
 


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