[llvm] r246354 - AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates

[Tom Stellard via llvm-commits]

Author: tstellar
Date: Fri Aug 28 20:58:21 2015
New Revision: 246354

URL: http://llvm.org/viewvc/llvm-project?rev=246354&view=rev
Log:
AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates

Summary:
We were assuming tha if the use operand had a sub-register that
the immediate was 64-bits, but this was breaking the case of
folding a 64-bit immediate into another 64-bit instruction.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12255

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp?rev=246354&r1=246353&r2=246354&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp Fri Aug 28 20:58:21 2015
@@ -211,8 +211,12 @@ static void foldOperand(MachineOperand &
 
     Imm = APInt(64, OpToFold.getImm());
 
+    const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode());
+    const TargetRegisterClass *FoldRC =
+        TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
+
     // Split 64-bit constants into 32-bits for folding.
-    if (UseOp.getSubReg()) {
+    if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
       if (UseRC->getSize() != 8)
         return;