[PATCH] D12465: AMDGPU/SI: Add verifier check for exec reads
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 18:53:21 PDT 2015
arsenm updated this revision to Diff 33508.
arsenm added a comment.
Set SALU bits on some pseudos
http://reviews.llvm.org/D12465
Files:
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIInstructions.td
Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -1850,7 +1850,7 @@
def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>;
} // end let hasSideEffects = 0, mayLoad = 0, mayStore = 0
-let hasSideEffects = 1 in {
+let hasSideEffects = 1, SALU = 1 in {
def SGPR_USE : InstSI <(outs),(ins), "", []>;
}
@@ -2041,7 +2041,9 @@
(outs SReg_64:$dst),
(ins),
"", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
->;
+> {
+ let SALU = 1;
+}
} // End Defs = [SCC]
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1416,6 +1416,16 @@
}
}
+ // Make sure we aren't losing exec uses in the td files. This mostly requires
+ // being careful when using let Uses to try to add other use registers.
+ if (!isBuiltinOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) {
+ const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC);
+ if (!Exec || !Exec->isImplicit()) {
+ ErrInfo = "VALU instruction does not implicitly read exec mask";
+ return false;
+ }
+ }
+
return true;
}
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