[PATCH] D12279: [mips][microMIPS] Implement ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions

[Zlatko Buljan via llvm-commits]

zbuljan added a comment.

We had to implement instructions because we introduced new decoder table for microMIPS32R6 16 bit instructions.
Introduction of new decoder table resulted in fail of disassembler tests for ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions.
Our solution was to add microMIPS32R6 implementation of this instructions.

Patch http://reviews.llvm.org/D11181 added new decoder table in it's first version, but later, after your first revision, we moved that code to patch http://reviews.llvm.org/D12279 (together with implementation).
Please can you check all diffs of patch http://reviews.llvm.org/D11181 (there is two diffs: Diff 1 29653 and Diff 2 32951).

New decoder table is also needed for instructions which are implemented in patch http://reviews.llvm.org/D11181 so we added dependancy to it.


http://reviews.llvm.org/D12279