[PATCH] D12093: [NVPTX] Support register copy from i16 to i32 register types

[Jingyue Wu via llvm-commits]

jingyue added inline comments.

================
Comment at: lib/Target/NVPTX/NVPTXInstrInfo.cpp:39-40
@@ -38,4 +38,4 @@
   const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
 
-  if (DestRC->getSize() != SrcRC->getSize())
-    report_fatal_error("Copy one register into another with a different width");
+  if (DestRC->getSize() != SrcRC->getSize()) {
+    // If the sizes differ it may be possible we are copying a i16 to a i32
----------------
jholewinski wrote:
> Right, we don't define i8 registers, so a load of an i8 has to be put in an i16 register.  We still shouldn't have a cross-class register copy here, though.
An even simpler test case is
```
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-unknown-unknown"

define void @ex(i8* noalias readonly %data, i32* %res) {
entry:
  %val = load i8, i8* %data
  %valext = zext i8 %val to i32
  store i32 %valext, i32* %res
  ret void
}

!nvvm.annotations = !{!0}
!0 = !{void (i8*, i32*)* @ex, !"kernel", i32 1}
```

`COPY` is generated when emitting `store`ing an `zext`ed load. 

Back up one step, is it right to emit an SDNode that returns int16reg when its corresponding IR instruction returns i8? Do ISel and other machine level passes assume some sort of consistency between IR types and SDNode types? 


http://reviews.llvm.org/D12093