[PATCH] D12325: Improve ISel using across lane addition reduction

[Jun Bum Lim via llvm-commits]

junbuml marked 11 inline comments as done.

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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8568
@@ -8566,1 +8567,3 @@
 
+/// Target-specific DAG combine for the across vector reduction.
+/// This function specifically handles the log2-shuffle pattern produced
----------------
. Changed the example using SDAG nodes.
. Specifically mentioned that this function handles the final step of vector reduction.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8583
@@ +8582,3 @@
+/// FIXME: Currently this function is implemented and tested specifically
+/// for the add reduction. We could also support other across lanes instructions
+/// available in AArch64, including SMAXV, SMINV, UMAXV, UMINV, SADDLV,
----------------
Add "FIXME" in comment.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8600
@@ +8599,3 @@
+  // The vector extract idx must constant zero because we only expect the final
+  // result of the reduction is placed in lane 0.
+  if (!isa<ConstantSDNode>(N1) || cast<ConstantSDNode>(N1)->getZExtValue())
----------------
Use "NumExpectedStep" and "CurStep" to iterate steps.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8628
@@ +8627,3 @@
+    }
+    // Check if this is one step of addition reduction.
+    // E.g.,
----------------
To check if an element is an UNDEF, we need to check if the mask is negative value. So, I'm checking   Mask[i] < 0.

================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:8633
@@ +8632,3 @@
+    //   %pre = add %cur, %shuffle
+    if (Shuffle.getOperand(0) != CurOp)
+      return SDValue();
----------------
Now I'm using PreOp and CurOp, instead of InputADD and ADD.


http://reviews.llvm.org/D12325