[PATCH] D12350: FastISel: Avoid adding a successor block twice for degenerate IR.

[Matthias Braun via llvm-commits]

MatzeB added a comment.

Yes this code is the result of an optnone attribute. But in any case this is legal IR and SelectionDAG handles this case in the same way[1], so there is no reason for FastISel to produce invalid MI.

[1] SelectionDAGBuilder.cpp:

  // Update successor info
  addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
  // TrueBB and FalseBB are always different unless the incoming IR is
  // degenerate. This only happens when running llc on weird IR.
  if (CB.TrueBB != CB.FalseBB)
    addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);


Repository:
  rL LLVM

http://reviews.llvm.org/D12350