[PATCH] D12364: [ARM] Hoist fabs/fneg above a conversion to float.
James Molloy via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 07:56:42 PDT 2015
jmolloy created this revision.
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This is especially visible in softfp mode, for example in the implementation of libm fabs/fneg functions. If we have:
%1 = vmovdrr r0, r1
%2 = fabs %1
then move the fabs before the vmovdrr:
%1 = and r1, #0x7FFFFFFF
%2 = vmovdrr r0, r1
This is never a lose, and could be a serious win because the vmovdrr may be followed by a vmovrrd, which would enable us to remove the conversion into FPRs completely.
We already do this for f32, but not for f64. Tests are added for both.
Repository:
rL LLVM
http://reviews.llvm.org/D12364
Files:
lib/Target/ARM/ARMInstrVFP.td
test/CodeGen/ARM/softfp-fabs-fneg.ll
Index: test/CodeGen/ARM/softfp-fabs-fneg.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/softfp-fabs-fneg.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK
+; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7--"
+
+define double @f(double %a) {
+ ; CHECK-LABEL: f:
+ ; CHECK: bfc r1, #31, #1
+ ; CHECK-NEXT: bx lr
+ %x = call double @llvm.fabs.f64(double %a) readnone
+ ret double %x
+}
+
+define float @g(float %a) {
+ ; CHECK-LABEL: g:
+ ; CHECK-THUMB: bic r0, r0, #-2147483648
+ ; CHECK-ARM: bfc r0, #31, #1
+ ; CHECK-NEXT: bx lr
+ %x = call float @llvm.fabs.f32(float %a) readnone
+ ret float %x
+}
+
+define double @h(double %a) {
+ ; CHECK-LABEL: h:
+ ; CHECK: eor r1, r1, #-2147483648
+ ; CHECK-NEXT: bx lr
+ %x = fsub nsz double -0.0, %a
+ ret double %x
+}
+
+define float @i(float %a) {
+ ; CHECK-LABEL: i:
+ ; CHECK: eor r0, r0, #-2147483648
+ ; CHECK-NEXT: bx lr
+ %x = fsub nsz float -0.0, %a
+ ret float %x
+}
+
+declare double @llvm.fabs.f64(double) readnone
+declare float @llvm.fabs.f32(float) readnone
Index: lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- lib/Target/ARM/ARMInstrVFP.td
+++ lib/Target/ARM/ARMInstrVFP.td
@@ -20,7 +20,6 @@
def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
-
//===----------------------------------------------------------------------===//
// Operand Definitions.
//
@@ -922,6 +921,22 @@
let isRegSequence = 1;
}
+// Hoist an fabs or a fneg of a value coming from integer registers
+// and do the fabs/fneg on the integer value. This is never a lose
+// and could enable the conversion to float to be removed completely.
+def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
+ (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
+ Requires<[IsARM]>;
+def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)),
+ (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>,
+ Requires<[IsThumb2]>;
+def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
+ (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>,
+ Requires<[IsARM]>;
+def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)),
+ (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>,
+ Requires<[IsThumb2]>;
+
let hasSideEffects = 0 in
def VMOVSRR : AVConv5I<0b11000100, 0b1010,
(outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
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