[PATCH] D12325: Improve ISel using across lane addition reduction

[James Molloy via llvm-commits]

Hi,

Thanks for working on this! It's long overdue. I'm hoping that long term,
this can get solved by Mohammed Sahid's work on hadd intrinsics, but I
don't know when that will land or be used by the loop vectoriser so this
looks like a good way forward in the meantime (x86 does similar matching).

I'll do a proper review in the morning.

Cheers,

James
On Tue, 25 Aug 2015 at 21:15, Jun Bum Lim via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> junbuml updated this revision to Diff 33109.
> junbuml added a comment.
>
> Thanks Chad for the quick review. I addressed your comments.
>
>
> http://reviews.llvm.org/D12325
>
> Files:
>   lib/Target/AArch64/AArch64ISelLowering.cpp
>   test/CodeGen/AArch64/aarch64-addv.ll
>
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