[PATCH] D11293: [mips] Remove incorrect DebugLoc entries from prologue.

Vladimir Radosavljevic via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 24 06:01:58 PDT 2015


vradosavljevic added a comment.

Machine instructions before Prologue/Epilogue Insertion:

  BB#0: derived from LLVM BB %entry
  	ADJCALLSTACKDOWN 16, %SP<imp-def,dead>, %SP<imp-use>; dbg:test.c:2:3
  	%AT<def> = LUi <ga:@.str>[TF=5]; dbg:test.c:2:3
  	%A0<def> = ADDiu %AT<kill>, <ga:@.str>[TF=6]; dbg:test.c:2:3
  	JAL <ga:@printf>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7>, %A0<imp-use,kill>, %SP<imp-def>, %V0<imp-def>, ...; dbg:test.c:2:3
  	ADJCALLSTACKUP 16, 0, %SP<imp-def,dead>, %SP<imp-use>; dbg:test.c:2:3
  	SW %V0<kill>, <fi#0>, 0; mem:ST4[FixedStack0] dbg:test.c:3:1
  	RetRA; dbg:test.c:3:1

Instructions in the prologue before this patch have the debug location from the first machine instruction (in this case debug location from ADJCALLSTACKDOWN 16). The first debug location is used to determine the prologue_end and because of that, it will be incorrectly positioned (in this case at the beginning of the prologue).

Machine instructions after Prologue/Epilogue Insertion before this patch:

  BB#0: derived from LLVM BB %entry
  	%SP<def> = ADDiu %SP, -24; dbg:test.c:2:3
  	CFI_INSTRUCTION <call frame instruction>; dbg:test.c:2:3
  	SW %RA<kill>, %SP, 20; mem:ST4[FixedStack1] dbg:test.c:2:3
  	CFI_INSTRUCTION <call frame instruction>; dbg:test.c:2:3
  	%AT<def> = LUi <ga:@.str>[TF=5]; dbg:test.c:2:3
  	%A0<def> = ADDiu %AT<kill>, <ga:@.str>[TF=6]; dbg:test.c:2:3
  	JAL <ga:@printf>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7>, %RA<imp-def,dead>, %A0<imp-use,kill>, %SP<imp-def>, %V0<imp-def>; dbg:test.c:2:3
  	SW %V0<kill>, %SP, 16; mem:ST4[FixedStack0] dbg:test.c:3:1
  	%RA<def> = LW %SP, 20; mem:LD4[FixedStack1] dbg:test.c:3:1
  	%SP<def> = ADDiu %SP, 24; dbg:test.c:3:1
  	RetRA; dbg:test.c:3:1

Machine instructions after Prologue/Epilogue Insertion with this patch:

  BB#0: derived from LLVM BB %entry
  	%SP<def> = ADDiu %SP, -24
  	CFI_INSTRUCTION <call frame instruction>
  	SW %RA<kill>, %SP, 20; mem:ST4[FixedStack1]
  	CFI_INSTRUCTION <call frame instruction>
  	%AT<def> = LUi <ga:@.str>[TF=5]; dbg:test.c:2:3
  	%A0<def> = ADDiu %AT<kill>, <ga:@.str>[TF=6]; dbg:test.c:2:3
  	JAL <ga:@printf>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7>, %RA<imp-def,dead>, %A0<imp-use,kill>, %SP<imp-def>, %V0<imp-def>; dbg:test.c:2:3
  	SW %V0<kill>, %SP, 16; mem:ST4[FixedStack0]
  	%RA<def> = LW %SP, 20; mem:LD4[FixedStack1] dbg:test.c:3:1
  	%SP<def> = ADDiu %SP, 24
  	RetRA; dbg:test.c:3:1


Repository:
  rL LLVM

http://reviews.llvm.org/D11293





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