[PATCH] D12116: [AArch64] Improve load/store optimizer to handle LDUR + LDR.

[Michael Zolotukhin via llvm-commits]

mzolotukhin added a comment.

Hi Chad,

I checked on a small testcase, and with this patch we do merge STUR and STR. There is one potential issue though: in some cases we intentionally split STP into two STUR/STR, as there is a big performance penalty if STP crosses a cache line (see e.g. `performSTORECombine` in `AArch64ISelLowering.cpp` and `getMemoryOpCost` in `AArch64TargetTransformInfo.cpp`). So, I think we might want to perform this combining only for non-temporal or known-to-be-well-aligned memory accesses. What do you think, does it make sense?

Thanks,
Michael


================
Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:455
@@ +454,3 @@
+    PairedOffset =
+        PairedIsUnscaled ? PairedOffset / MemSize : PairedOffset * MemSize;
+  }
----------------
This looks strange. Is it expected that scaled and unscaled offset differ by `MemSize^2`? (in one case you multiply by `MemSize`, in the other - divide)

================
Comment at: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:708
@@ +707,3 @@
+        int MemSize = getMemSize(MI);
+        MIOffset = MIIsUnscaled ? MIOffset / MemSize : MIOffset * MemSize;
+      }
----------------
Same here.


Repository:
  rL LLVM

http://reviews.llvm.org/D12116