[PATCH] D12255: AMDGPU/SI: Fix some invaild assumptions when folding 64-bit immediates

[Tom Stellard via llvm-commits]

tstellarAMD created this revision.
tstellarAMD added a reviewer: arsenm.
tstellarAMD added a subscriber: llvm-commits.
Herald added a subscriber: arsenm.

We were assuming tha if the use operand had a sub-register that
the immediate was 64-bits, but this was breaking the case of
folding a 64-bit immediate into another 64-bit instruction.

http://reviews.llvm.org/D12255

Files:
  lib/Target/AMDGPU/SIFoldOperands.cpp

Index: lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- lib/Target/AMDGPU/SIFoldOperands.cpp
+++ lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -211,8 +211,12 @@
 
     Imm = APInt(64, OpToFold.getImm());
 
+    const MCInstrDesc &FoldDesc = TII->get(OpToFold.getParent()->getOpcode());
+    const TargetRegisterClass *FoldRC =
+        TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
+
     // Split 64-bit constants into 32-bits for folding.
-    if (UseOp.getSubReg()) {
+    if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
       if (UseRC->getSize() != 8)
         return;
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D12255.32880.patch
Type: text/x-patch
Size: 634 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20150821/1bcedb3b/attachment.bin>