[PATCH] D11628: [mips][microMIPS] Implement CACHEE and PREFE instructions

[Daniel Sanders via llvm-commits]

dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

LGTM with some nits.


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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp:773-774
@@ +772,4 @@
+getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
+                      SmallVectorImpl<MCFixup> &Fixups,
+                      const MCSubtargetInfo &STI) const {
+  // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
----------------
Indentation


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Comment at: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h:176-177
@@ -175,1 +175,4 @@
+  unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
----------------
Indentation

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Comment at: lib/Target/Mips/MicroMipsInstrFormats.td:925
@@ -924,1 +924,3 @@
 
+class CACHE_PREFE_FM_MM<bits<6> op, bits<3> funct> : MMArch {
+  bits<21> addr;
----------------
This doesn't follow the naming convention but that's ok since microMIPS in general hasn't migrated yet.

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Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:110
@@ +109,3 @@
+  let PrintMethod = "printMemOperand";
+  let MIOperandInfo = (ops GPR32, simm12);
+  let EncoderMethod = "getMemEncodingMMImm9";
----------------
Shouldn't it be simm9?


http://reviews.llvm.org/D11628