[PATCH] D11801: [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions

[Daniel Sanders via llvm-commits]

dsanders added inline comments.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:201-226
@@ -200,2 +200,28 @@
 
+class STORE_FM_MMR6<bits<6> op> {
+  bits<5> rt;
+  bits<21> addr;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = op;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = addr{20-16};
+  let Inst{15-0}  = addr{15-0};
+}
+
+class STORE_EVA_FM_MMR6<bits<3> funct> {
+  bits<5> rt;
+  bits<21> addr;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b011000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = addr{20-16}; // base
+  let Inst{15-12} = 0b1010;
+  let Inst{11-9} = funct;
+  let Inst{8-0}  = addr{8-0}; // offset
+}
+
 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
----------------
dsanders wrote:
> Please break out the fields of addr using variables.
> 
> For example:
>   bits<21> addr;
>   let Inst{20-16} = addr{20-16};
>   let Inst{15-0}  = addr{15-0};
> should be something like:
>   bits<21> addr;
>   bits<5> base = addr{20-16};
>   bits<16> offset = addr{15-0};
>   let Inst{20-16} = base;
>   let Inst{15-0}  = offset;
> 
> This helps to document the unusual encoding we use for addr fields.
Forgot to say: These format classes don't follow the naming convention.

'STORE_EVA_FM_MMR6' should be POOL32C_<something>_FM_MMR6

STORE_FM_MMR6 ought to be SB32_<something>_FM_MMR6 and SH32_<something>_FM_MMR6 but it's good to share the code. Maybe SX32_... or SB32_SH32_...


http://reviews.llvm.org/D11801