[llvm] r245554 - [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions

Zoran Jovanovic via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 20 04:51:49 PDT 2015


Author: zjovanovic
Date: Thu Aug 20 06:51:49 2015
New Revision: 245554

URL: http://llvm.org/viewvc/llvm-project?rev=245554&view=rev
Log:
[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions
Differential Revision: http://reviews.llvm.org/D10955

Modified:
    llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
    llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt
    llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
    llvm/trunk/test/MC/Mips/micromips32r6/valid.s
    llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
    llvm/trunk/test/MC/Mips/micromips64r6/valid.s

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt?rev=245554&r1=245553&r2=245554&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6.txt Thu Aug 20 06:51:49 2015
@@ -8,6 +8,24 @@
 
 0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100
 
+0x6f 0x83 # CHECK: addiur1sp $7, 4
+
+0x6f 0x7e # CHECK: addiur2 $6, $7, -1
+
+0x6f 0x76 # CHECK: addiur2 $6, $7, 12
+
+0x4c 0xfc # CHECK: addius5 $7, -2
+
+0x4f 0xff # CHECK: addiusp -1028
+
+0x4f 0xfd # CHECK: addiusp -1032
+
+0x4c 0x01 # CHECK: addiusp 1024
+
+0x4c 0x03 # CHECK: addiusp 1028
+
+0x4f 0xf9 # CHECK: addiusp -16
+
 0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
 
 0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1

Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt?rev=245554&r1=245553&r2=245554&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips64r6.txt Thu Aug 20 06:51:49 2015
@@ -1,5 +1,23 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 -mattr=micromips | FileCheck %s
 
+0x6f 0x83 # CHECK: addiur1sp $7, 4
+
+0x6f 0x7e # CHECK: addiur2 $6, $7, -1
+
+0x6f 0x76 # CHECK: addiur2 $6, $7, 12
+
+0x4c 0xfc # CHECK: addius5 $7, -2
+
+0x4f 0xff # CHECK: addiusp -1028
+
+0x4f 0xfd # CHECK: addiusp -1032
+
+0x4c 0x01 # CHECK: addiusp 1024
+
+0x4c 0x03 # CHECK: addiusp 1028
+
+0x4f 0xf9 # CHECK: addiusp -16
+
 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
 
 0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4

Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=245554&r1=245553&r2=245554&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Thu Aug 20 06:51:49 2015
@@ -1,6 +1,13 @@
 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
 # RUN: FileCheck %s < %t1
 
+  addiur1sp $7, 260        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addiur1sp $7, 241        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value
+  addiur1sp $8, 240        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  addiur2 $9, $7, -1       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  addiur2 $6, $7, 10       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addius5 $7, 9            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addiusp 1032             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   break 1024               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   break 1023, 1024         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   ei $32                   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=245554&r1=245553&r2=245554&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Thu Aug 20 06:51:49 2015
@@ -5,6 +5,15 @@
   addiu $3, $4, 1234       # CHECK: addiu $3, $4, 1234  # encoding: [0x30,0x64,0x04,0xd2]
   addu $3, $4, $5          # CHECK: addu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x50]
   addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0x78,0x80,0x00,0x19]
+  addiur1sp $7, 4          # CHECK: addiur1sp $7, 4     # encoding: [0x6f,0x83]
+  addiur2 $6, $7, -1       # CHECK: addiur2 $6, $7, -1  # encoding: [0x6f,0x7e]
+  addiur2 $6, $7, 12       # CHECK: addiur2 $6, $7, 12  # encoding: [0x6f,0x76]
+  addius5 $7, -2           # CHECK: addius5 $7, -2      # encoding: [0x4c,0xfc]
+  addiusp -1028            # CHECK: addiusp -1028       # encoding: [0x4f,0xff]
+  addiusp -1032            # CHECK: addiusp -1032       # encoding: [0x4f,0xfd]
+  addiusp 1024             # CHECK: addiusp 1024        # encoding: [0x4c,0x01]
+  addiusp 1028             # CHECK: addiusp 1028        # encoding: [0x4c,0x03]
+  addiusp -16              # CHECK: addiusp -16         # encoding: [0x4f,0xf9]
   aluipc $3, 56            # CHECK: aluipc $3, 56       # encoding: [0x78,0x7f,0x00,0x38]
   and $3, $4, $5           # CHECK: and $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x50]
   andi $3, $4, 1234        # CHECK: andi $3, $4, 1234   # encoding: [0xd0,0x64,0x04,0xd2]

Modified: llvm/trunk/test/MC/Mips/micromips64r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/invalid.s?rev=245554&r1=245553&r2=245554&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/invalid.s Thu Aug 20 06:51:49 2015
@@ -1,6 +1,13 @@
 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1
 # RUN: FileCheck %s < %t1
 
+  addiur1sp $7, 260        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addiur1sp $7, 241        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value
+  addiur1sp $8, 240        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  addiur2 $9, $7, -1       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  addiur2 $6, $7, 10       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addius5 $7, 9            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  addiusp 1032             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   ddiv $32, $4, $5         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   ddiv $3, $34, $5         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   ddiv $3, $4, $35         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

Modified: llvm/trunk/test/MC/Mips/micromips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=245554&r1=245553&r2=245554&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips64r6/valid.s Thu Aug 20 06:51:49 2015
@@ -1,6 +1,15 @@
 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=micromips | FileCheck %s
 a:
         .set noat
+        addiur1sp $7, 4          # CHECK: addiur1sp $7, 4     # encoding: [0x6f,0x83]
+        addiur2 $6, $7, -1       # CHECK: addiur2 $6, $7, -1  # encoding: [0x6f,0x7e]
+        addiur2 $6, $7, 12       # CHECK: addiur2 $6, $7, 12  # encoding: [0x6f,0x76]
+        addius5 $7, -2           # CHECK: addius5 $7, -2      # encoding: [0x4c,0xfc]
+        addiusp -1028            # CHECK: addiusp -1028       # encoding: [0x4f,0xff]
+        addiusp -1032            # CHECK: addiusp -1032       # encoding: [0x4f,0xfd]
+        addiusp 1024             # CHECK: addiusp 1024        # encoding: [0x4c,0x01]
+        addiusp 1028             # CHECK: addiusp 1028        # encoding: [0x4c,0x03]
+        addiusp -16              # CHECK: addiusp -16         # encoding: [0x4f,0xf9]
         daui $3, $4, 5           # CHECK: daui $3, $4, 5      # encoding: [0xf0,0x64,0x00,0x05]
         dahi $3, 4               # CHECK: dahi $3, 4          # encoding: [0x42,0x23,0x00,0x04]
         dati $3, 4               # CHECK: dati $3, 4          # encoding: [0x42,0x03,0x00,0x04]




More information about the llvm-commits mailing list