[PATCH] D12154: [x86] invert logic for attribute 'FeatureFastUAMem'

[Sanjay Patel via llvm-commits]

spatel added a comment.

Thanks, Sean and Zia. Certainly appreciate the detailed analysis.

So it sounds like we're not completely broken. The attributes themselves may be sufficient to generate the code as we want to, and they are even mostly applied correctly for each CPU. I'll fix the AMD chips as much as possible in a follow-on patch.

The bugs are as I noted in the FIXME/TODO comments in the lowering itself. We should probably also have the AVX or SSE4.2 attribute imply that IsUAMemUnder32Slow is false. That way if someone has only specified -mavx without a particular -mcpu, they would get the benefit of larger unaligned memory accesses. Alternatively, -mavx might bump the default CPU model from Merom to Sandybridge.

Regarding crossing cachelines: the current behavior is that we don't take that into account, and that's probably how it will remain...unless for example, a front-end starts specifying 'align 64' in the IR.


http://reviews.llvm.org/D12154