[PATCH] D12145: [ARM][AArch64] Turn on by default interleaved access lowering

[silviu.baranga@arm.com via llvm-commits]

sbaranga created this revision.
sbaranga added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.

Interleaved access lowering removes a memory operation and a
sequence of vector shuffles and replaces it with a series of
memory operations. This should be always beneficial.

This pass in only enabled on ARM/AArch64.

http://reviews.llvm.org/D12145

Files:
  lib/CodeGen/InterleavedAccessPass.cpp
  test/CodeGen/ARM/vext.ll
  test/CodeGen/ARM/vpadd.ll

Index: test/CodeGen/ARM/vpadd.ll
===================================================================
--- test/CodeGen/ARM/vpadd.ll
+++ test/CodeGen/ARM/vpadd.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
 
 define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpaddi8:
Index: test/CodeGen/ARM/vext.ll
===================================================================
--- test/CodeGen/ARM/vext.ll
+++ test/CodeGen/ARM/vext.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
 
 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextd:
Index: lib/CodeGen/InterleavedAccessPass.cpp
===================================================================
--- lib/CodeGen/InterleavedAccessPass.cpp
+++ lib/CodeGen/InterleavedAccessPass.cpp
@@ -52,7 +52,7 @@
 static cl::opt<bool> LowerInterleavedAccesses(
     "lower-interleaved-accesses",
     cl::desc("Enable lowering interleaved accesses to intrinsics"),
-    cl::init(false), cl::Hidden);
+    cl::init(true), cl::Hidden);
 
 static unsigned MaxFactor; // The maximum supported interleave factor.
 


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