[PATCH] D12105: [ARM] Add instruction selection patterns for vmin/vmax

[James Molloy via llvm-commits]

jmolloy requested changes to this revision.
jmolloy added a comment.
This revision now requires changes to proceed.

This isn't the best way to do this. Instead, we should be modifying the definition of VMINs and friends to match a "smin" node instead of a "int_arm_neon_smin".

Then, we should add lowering to ARMISelLowering.cpp to map from arm_neon_vmins to ISD::SMIN. See how I did it for FMINNAN/FMINNUM as an example.

I've noticed that you've copied this mechanism from the AArch64 backend. Mea culpa - I obviously did it suboptimally there too. Either change AArch64 too as a followup or raise a PR and I'll get around to it.

Cheers,

James


http://reviews.llvm.org/D12105