[llvm] r245384 - MIR Parser: Return true on error when parsing standalone registers.
Alex Lorenz via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 18 15:57:36 PDT 2015
Author: arphaman
Date: Tue Aug 18 17:57:36 2015
New Revision: 245384
URL: http://llvm.org/viewvc/llvm-project?rev=245384&view=rev
Log:
MIR Parser: Return true on error when parsing standalone registers.
Added:
llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir
Modified:
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=245384&r1=245383&r2=245384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Tue Aug 18 17:57:36 2015
@@ -647,7 +647,7 @@ bool MIParser::parseStandaloneNamedRegis
if (Token.isNot(MIToken::NamedRegister))
return error("expected a named register");
if (parseRegister(Reg))
- return 0;
+ return true;
lex();
if (Token.isNot(MIToken::Eof))
return error("expected end of string after the register reference");
@@ -659,7 +659,7 @@ bool MIParser::parseStandaloneVirtualReg
if (Token.isNot(MIToken::VirtualRegister))
return error("expected a virtual register");
if (parseRegister(Reg))
- return 0;
+ return true;
lex();
if (Token.isNot(MIToken::Eof))
return error("expected end of string after the register reference");
Added: llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir?rev=245384&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/standalone-register-error.mir Tue Aug 18 17:57:36 2015
@@ -0,0 +1,24 @@
+# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
+--- |
+ define i32 @test(i32 %a) {
+ body:
+ ret i32 %a
+ }
+...
+---
+name: test
+isSSA: true
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gr32 }
+liveins:
+# CHECK: [[@LINE+1]]:13: unknown register name 'register'
+ - { reg: '%register', virtual-reg: '%0' }
+body: |
+ bb.0.body:
+ liveins: %edi
+
+ %0 = COPY %edi
+ %eax = COPY %0
+ RETQ %eax
+...
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