[llvm] r245198 - Remove hand-rolled matching for fmin and fmax.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 18 11:35:53 PDT 2015
Hey James,
If I read this correctly, we can't fold fpext anymore, right? Not a big
deal right now, as the main case where I see this being useful is a
promoted f16 min/max, and that's not even caught currently.
Do you think we should do something similar in the builder? If so, let's
file a PR!
-Ahmed
On Mon, Aug 17, 2015 at 12:13 AM, James Molloy via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: jamesm
> Date: Mon Aug 17 02:13:20 2015
> New Revision: 245198
>
> URL: http://llvm.org/viewvc/llvm-project?rev=245198&view=rev
> Log:
> Remove hand-rolled matching for fmin and fmax.
>
> SDAGBuilder now does this all for us.
>
> Modified:
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=245198&r1=245197&r2=245198&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Mon Aug 17
> 02:13:20 2015
> @@ -393,6 +393,8 @@ AArch64TargetLowering::AArch64TargetLowe
> setOperationAction(ISD::FROUND, Ty, Legal);
> setOperationAction(ISD::FMINNUM, Ty, Legal);
> setOperationAction(ISD::FMAXNUM, Ty, Legal);
> + setOperationAction(ISD::FMINNAN, Ty, Legal);
> + setOperationAction(ISD::FMAXNAN, Ty, Legal);
> }
>
> setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
> @@ -484,7 +486,6 @@ AArch64TargetLowering::AArch64TargetLowe
>
> setTargetDAGCombine(ISD::SELECT);
> setTargetDAGCombine(ISD::VSELECT);
> - setTargetDAGCombine(ISD::SELECT_CC);
>
> setTargetDAGCombine(ISD::INTRINSIC_VOID);
> setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
> @@ -3826,32 +3827,6 @@ SDValue AArch64TargetLowering::LowerSETC
> }
> }
>
> -/// A SELECT_CC operation is really some kind of max or min if both
> values being
> -/// compared are, in some sense, equal to the results in either case.
> However,
> -/// it is permissible to compare f32 values and produce directly extended
> f64
> -/// values.
> -///
> -/// Extending the comparison operands would also be allowed, but is less
> likely
> -/// to happen in practice since their use is right here. Note that
> truncate
> -/// operations would *not* be semantically equivalent.
> -static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
> - if (Cmp == Result)
> - return (Cmp.getValueType() == MVT::f32 ||
> - Cmp.getValueType() == MVT::f64);
> -
> - ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
> - ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
> - if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
> - Result.getValueType() == MVT::f64) {
> - bool Lossy;
> - APFloat CmpVal = CCmp->getValueAPF();
> - CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
> &Lossy);
> - return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
> - }
> -
> - return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0)
> == Cmp;
> -}
> -
> SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue
> LHS,
> SDValue RHS, SDValue TVal,
> SDValue FVal, SDLoc dl,
> @@ -9124,75 +9099,6 @@ static SDValue performSelectCombine(SDNo
> return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1),
> N->getOperand(2));
> }
>
> -/// performSelectCCCombine - Target-specific DAG combining for
> ISD::SELECT_CC
> -/// to match FMIN/FMAX patterns.
> -static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
> - // Try to use FMIN/FMAX instructions for FP selects like "x < y ? x :
> y".
> - // Unless the NoNaNsFPMath option is set, be careful about NaNs:
> - // vmax/vmin return NaN if either operand is a NaN;
> - // only do the transformation when it matches that behavior.
> -
> - SDValue CondLHS = N->getOperand(0);
> - SDValue CondRHS = N->getOperand(1);
> - SDValue LHS = N->getOperand(2);
> - SDValue RHS = N->getOperand(3);
> - ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
> -
> - unsigned Opcode;
> - bool IsReversed;
> - if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
> - selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
> - IsReversed = false; // x CC y ? x : y
> - } else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
> - selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
> - IsReversed = true ; // x CC y ? y : x
> - } else {
> - return SDValue();
> - }
> -
> - bool IsUnordered = false, IsOrEqual;
> - switch (CC) {
> - default:
> - return SDValue();
> - case ISD::SETULT:
> - case ISD::SETULE:
> - IsUnordered = true;
> - case ISD::SETOLT:
> - case ISD::SETOLE:
> - case ISD::SETLT:
> - case ISD::SETLE:
> - IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC ==
> ISD::SETULE);
> - Opcode = IsReversed ? ISD::FMAXNAN : ISD::FMINNAN;
> - break;
> -
> - case ISD::SETUGT:
> - case ISD::SETUGE:
> - IsUnordered = true;
> - case ISD::SETOGT:
> - case ISD::SETOGE:
> - case ISD::SETGT:
> - case ISD::SETGE:
> - IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC ==
> ISD::SETUGE);
> - Opcode = IsReversed ? ISD::FMINNAN : ISD::FMAXNAN;
> - break;
> - }
> -
> - // If LHS is NaN, an ordered comparison will be false and the result
> will be
> - // the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by
> checking
> - // that LHS != NaN. Likewise, for unordered comparisons, check for RHS
> != NaN.
> - if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
> - return SDValue();
> -
> - // For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be
> true,
> - // but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can
> only be
> - // used for unsafe math or if one of the operands is known to be
> nonzero.
> - if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
> - !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
> - return SDValue();
> -
> - return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
> -}
> -
> /// Get rid of unnecessary NVCASTs (that don't change the type).
> static SDValue performNVCASTCombine(SDNode *N) {
> if (N->getValueType(0) == N->getOperand(0).getValueType())
> @@ -9233,8 +9139,6 @@ SDValue AArch64TargetLowering::PerformDA
> return performSelectCombine(N, DCI);
> case ISD::VSELECT:
> return performVSelectCombine(N, DCI.DAG);
> - case ISD::SELECT_CC:
> - return performSelectCCCombine(N, DCI.DAG);
> case ISD::STORE:
> return performSTORECombine(N, DCI, DAG, Subtarget);
> case AArch64ISD::BRCOND:
>
>
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