[PATCH] D12095: propagate fast-math-flags on DAG nodes
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 17 18:11:30 PDT 2015
spatel created this revision.
spatel added reviewers: hfinkel, escha, nlewycky.
spatel added a subscriber: llvm-commits.
After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, so I enabled them at r243687. However, Escha soon notified us of a bug not covered by any in-tree regression tests: if we don't propagate the flags, we may fail to CSE DAG nodes because differing FMF causes them to not match. There is one test case in this patch to prove that point. :)
This patch hopes to fix or leave a 'TODO' for all of the in-tree places where we create nodes that are FMF-capable. I did this by putting an assert in SelectionDAG.getNode() to find any FMF-capable node that was being created without FMF ( D11807 ). I then ran all regression tests and test-suite and confirmed that everything passes.
This patch exposes remaining work to get DAG FMF to be fully functional: (1) add the flags to non-binary nodes such as FCMP, FMA and FNEG; (2) add the flags to intrinsics; (3) use the flags as conditions for transforms rather than the current global settings.
Note: I didn't try to locate all the spots where the existing nsw / nuw / exact flags should be propagated, but it doesn't look like those are handled correctly either. Maybe it doesn't matter as much? Nobody has reported a problem from those, and they've been in the DAG for over a year ( http://reviews.llvm.org/rL210467 ).
http://reviews.llvm.org/D12095
Files:
include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
lib/Target/AMDGPU/R600ISelLowering.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/Mips/MipsSEISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/dag-fmf-cse.ll
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