[llvm] r244594 - [AArch64] Replace the custom AArch64ISD::FMIN/MAX nodes with ISD::FMINNAN/MAXNAN
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 14 14:11:43 PDT 2015
On Fri, Aug 14, 2015 at 2:11 AM, James Molloy <James.Molloy at arm.com> wrote:
> Hi Ahmed,
>
> Nice catch, thanks!
>
> I’ve conditionalised this for non-f16 in r245035 and added a test.
>
> fmin/fmax won’t be generated for f16 now and won’t currently be when
> D12015 lands, as D12015 checks that fmin/fmax is legal or custom - it
> doesn’t handle promoted types. This is an obvious improvement I could make.
>
Ah, right. Thanks for the fix!
-Ahmed
> Cheers,
>
> James
>
> On 13 Aug 2015, at 23:32, Ahmed Bougacha <ahmed.bougacha at gmail.com> wrote:
>
>
> On Tue, Aug 11, 2015 at 5:06 AM, James Molloy via llvm-commits <
> llvm-commits at lists.llvm.org>wrote:
>
>> Author: jamesm
>> Date: Tue Aug 11 07:06:33 2015
>> New Revision: 244594
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=244594&view=rev
>> Log:
>> [AArch64] Replace the custom AArch64ISD::FMIN/MAX nodes with
>> ISD::FMINNAN/MAXNAN
>>
>> NFCI. This just removes custom ISDNodes that are no longer needed.
>>
>> Modified:
>> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
>> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=244594&r1=244593&r2=244594&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Aug 11
>> 07:06:33 2015
>> @@ -679,6 +679,11 @@ void AArch64TargetLowering::addTypeForNE
>> ISD::SABSDIFF, ISD::UABSDIFF})
>> setOperationAction(Opcode, VT.getSimpleVT(), Legal);
>>
>> + // F[MIN|MAX]NAN are available for all FP NEON types.
>> + if (VT.isFloatingPoint())
>> + for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN})
>> + setOperationAction(Opcode, VT.getSimpleVT(), Legal);
>> +
>>
>
> f16 shouldn't be Legal (the Expand default is fine, but Promote with the
> other f16 setOperationActions is better).
>
> I guess this can't fire without D12015; when you land that, can you fix
> this and add an f{min,max}nan testcase to f16-instructions.ll (or
> elsewhere)?
>
> Thanks!
>
> -Ahmed
>
>
>> if (Subtarget->isLittleEndian()) {
>> for (unsigned im = (unsigned)ISD::PRE_INC;
>> im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
>> @@ -818,8 +823,6 @@ const char *AArch64TargetLowering::getTa
>> case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
>> case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
>> case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
>> - case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
>> - case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
>> case AArch64ISD::DUP: return "AArch64ISD::DUP";
>> case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
>> case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
>> @@ -8219,10 +8222,10 @@ static SDValue performIntrinsicCombine(S
>> case Intrinsic::aarch64_neon_umaxv:
>> return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
>> case Intrinsic::aarch64_neon_fmax:
>> - return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
>> + return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0),
>> N->getOperand(1), N->getOperand(2));
>> case Intrinsic::aarch64_neon_fmin:
>> - return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
>> + return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),
>> N->getOperand(1), N->getOperand(2));
>> case Intrinsic::aarch64_neon_sabd:
>> return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
>> @@ -9147,7 +9150,7 @@ static SDValue performSelectCCCombine(SD
>> case ISD::SETLT:
>> case ISD::SETLE:
>> IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC ==
>> ISD::SETULE);
>> - Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
>> + Opcode = IsReversed ? ISD::FMAXNAN : ISD::FMINNAN;
>> break;
>>
>> case ISD::SETUGT:
>> @@ -9158,7 +9161,7 @@ static SDValue performSelectCCCombine(SD
>> case ISD::SETGT:
>> case ISD::SETGE:
>> IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC ==
>> ISD::SETUGE);
>> - Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
>> + Opcode = IsReversed ? ISD::FMINNAN : ISD::FMAXNAN;
>> break;
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h?rev=244594&r1=244593&r2=244594&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h Tue Aug 11
>> 07:06:33 2015
>> @@ -66,10 +66,6 @@ enum NodeType : unsigned {
>> // Floating point comparison
>> FCMP,
>>
>> - // Floating point max and min instructions.
>> - FMAX,
>> - FMIN,
>> -
>> // Scalar extract
>> EXTR,
>>
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=244594&r1=244593&r2=244594&view=diff
>>
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue Aug 11 07:06:33
>> 2015
>> @@ -182,9 +182,6 @@ def AArch64threadpointer : SDNode<"AArch
>>
>> def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
>>
>> -def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
>> -def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
>> -
>> def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
>> def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8",
>> SDT_AArch64DupLane>;
>> def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16",
>> SDT_AArch64DupLane>;
>> @@ -2506,18 +2503,18 @@ let SchedRW = [WriteFDiv] in {
>> defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
>> }
>> defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm",
>> int_aarch64_neon_fmaxnm>;
>> -defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
>> +defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
>> defm FMINNM : TwoOperandFPData<0b0111, "fminnm",
>> int_aarch64_neon_fminnm>;
>> -defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
>> +defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
>> let SchedRW = [WriteFMul] in {
>> defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
>> defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
>> }
>> defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
>>
>> -def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
>> +def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
>> (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
>> -def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
>> +def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
>> (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
>> def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64
>> FPR64:$Rm))),
>> (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
>> @@ -2809,11 +2806,11 @@ defm FDIV : SIMDThreeSameVectorFP<1,0
>> defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp",
>> int_aarch64_neon_fmaxnmp>;
>> defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm",
>> int_aarch64_neon_fmaxnm>;
>> defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp",
>> int_aarch64_neon_fmaxp>;
>> -defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
>> +defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", fmaxnan>;
>> defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp",
>> int_aarch64_neon_fminnmp>;
>> defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm",
>> int_aarch64_neon_fminnm>;
>> defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp",
>> int_aarch64_neon_fminp>;
>> -defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
>> +defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", fminnan>;
>>
>> // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because
>> the
>> // instruction expects the addend first, while the fma intrinsic puts it
>> last.
>>
>>
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