[llvm] r245035 - [AArch64] FMINNAN/FMAXNAN on f16 is not legal.

[James Molloy via llvm-commits]

Author: jamesm
Date: Fri Aug 14 04:08:50 2015
New Revision: 245035

URL: http://llvm.org/viewvc/llvm-project?rev=245035&view=rev
Log:
[AArch64] FMINNAN/FMAXNAN on f16 is not legal.

Spotted by Ahmed - in r244594 I inadvertently marked f16 min/max as legal.

I've reverted it here, and marked min/max on scalar f16's as promote. I've also added a testcase. The test just checks that the compiler doesn't fall over - it doesn't create fmin nodes for f16 yet.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=245035&r1=245034&r2=245035&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Aug 14 04:08:50 2015
@@ -301,6 +301,8 @@ AArch64TargetLowering::AArch64TargetLowe
   setOperationAction(ISD::FTRUNC,      MVT::f16,  Promote);
   setOperationAction(ISD::FMINNUM,     MVT::f16,  Promote);
   setOperationAction(ISD::FMAXNUM,     MVT::f16,  Promote);
+  setOperationAction(ISD::FMINNAN,     MVT::f16,  Promote);
+  setOperationAction(ISD::FMAXNAN,     MVT::f16,  Promote);
 
   // v4f16 is also a storage-only type, so promote it to v4f32 when that is
   // known to be safe.
@@ -681,8 +683,8 @@ void AArch64TargetLowering::addTypeForNE
                             ISD::SABSDIFF, ISD::UABSDIFF})
       setOperationAction(Opcode, VT.getSimpleVT(), Legal);
 
-  // F[MIN|MAX][NUM|NAN] are available for all FP NEON types.
-  if (VT.isFloatingPoint())
+  // F[MIN|MAX][NUM|NAN] are available for all FP NEON types (not f16 though!).
+  if (VT.isFloatingPoint() && VT.getVectorElementType() != MVT::f16)
     for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
                             ISD::FMINNUM, ISD::FMAXNUM})
       setOperationAction(Opcode, VT.getSimpleVT(), Legal);

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll?rev=245035&r1=245034&r2=245035&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fmax.ll Fri Aug 14 04:08:50 2015
@@ -51,3 +51,14 @@ define i64 @test_integer(i64  %in) {
   %val = select i1 %cmp, i64 0, i64 %in
   ret i64 %val
 }
+
+define float @test_f16(half %in) {
+; CHECK-LABEL: test_f16:
+  %cmp = fcmp nnan ult half %in, 0.000000e+00
+  %val = select i1 %cmp, half %in, half 0.000000e+00
+  %longer = fpext half %val to float
+  ret float %longer
+; FIXME: It'd be nice for this to create an fmin instruction!
+; CHECK: fcvt
+; CHECK: fcsel
+}