[PATCH] D12015: [SDAG] Generate FMINNUM/FMAXNUM/FMINNAN/FMAXNAN from SDAGBuilder

[James Molloy via llvm-commits]

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These only get generated if the target supports them. If one of the variants is not legal and the other is, and it is safe to do so, the other variant will be emitted.

For example on AArch32 (V8), we have scalar fminnm but not fmin.

Fix up a couple of tests while we're here - one now produces better code, and the other was just plain wrong to start with.

This is tested by the fact that both ARM and AArch64 mark these nodes as legal.

I know this is basically mechanical, but as it's in the target independent layer I'd appreciate peoples' eyes on it.

Repository:
  rL LLVM

http://reviews.llvm.org/D12015

Files:
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  test/CodeGen/AArch64/arm64-fmax-safe.ll
  test/CodeGen/ARM/vminmaxnm.ll

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