[llvm] r244858 - [CodeGen] When Promoting, don't extend the 2nd FCOPYSIGN operand.

[Ahmed Bougacha via llvm-commits]

Author: ab
Date: Wed Aug 12 20:09:43 2015
New Revision: 244858

URL: http://llvm.org/viewvc/llvm-project?rev=244858&view=rev
Log:
[CodeGen] When Promoting, don't extend the 2nd FCOPYSIGN operand.

We don't care about its type, and there's even a combine that'll fold
away the FP_EXTEND if we let it run. However, until it does, we'll have
something broken like:
  (f32 (fp_extend (f64 v)))

Scalar f16 follow-up to r243924.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=244858&r1=244857&r2=244858&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 12 20:09:43 2015
@@ -4278,7 +4278,6 @@ void SelectionDAGLegalize::PromoteNode(S
   case ISD::FREM:
   case ISD::FMINNUM:
   case ISD::FMAXNUM:
-  case ISD::FCOPYSIGN:
   case ISD::FPOW: {
     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
     Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
@@ -4297,6 +4296,7 @@ void SelectionDAGLegalize::PromoteNode(S
                     DAG.getIntPtrConstant(0, dl)));
     break;
   }
+  case ISD::FCOPYSIGN:
   case ISD::FPOWI: {
     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
     Tmp2 = Node->getOperand(1);

Modified: llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll?rev=244858&r1=244857&r2=244858&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/f16-instructions.ll Wed Aug 12 20:09:43 2015
@@ -666,17 +666,48 @@ define half @test_maxnum(half %a, half %
 }
 
 ; CHECK-LABEL: test_copysign:
-; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: str h1, [sp, #8]
+; CHECK-NEXT: ldr x8, [sp, #8]
 ; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
-; CHECK-NEXT: bit.16b v0, v1, v2
+; CHECK-NEXT: fabs s0, s0
+; CHECK-NEXT: fneg s1, s0
+; CHECK-NEXT: lsl x8, x8, #48
+; CHECK-NEXT: cmp  x8, #0
+; CHECK-NEXT: fcsel s0, s1, s0, lt
 ; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: add sp, sp, #16
 ; CHECK-NEXT: ret
 define half @test_copysign(half %a, half %b) #0 {
   %r = call half @llvm.copysign.f16(half %a, half %b)
   ret half %r
 }
 
+; CHECK-LABEL: test_copysign_f32:
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
+; CHECK-NEXT: bit.16b v0, v1, v2
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_copysign_f32(half %a, float %b) #0 {
+  %tb = fptrunc float %b to half
+  %r = call half @llvm.copysign.f16(half %a, half %tb)
+  ret half %r
+}
+
+; CHECK-LABEL: test_copysign_f64:
+; CHECK-NEXT: fcvt s1, d1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
+; CHECK-NEXT: bit.16b v0, v1, v2
+; CHECK-NEXT: fcvt h0, s0
+; CHECK-NEXT: ret
+define half @test_copysign_f64(half %a, double %b) #0 {
+  %tb = fptrunc double %b to half
+  %r = call half @llvm.copysign.f16(half %a, half %tb)
+  ret half %r
+}
+
 ; CHECK-LABEL: test_floor:
 ; CHECK-NEXT: fcvt [[FLOAT32:s[0-9]+]], h0
 ; CHECK-NEXT: frintm [[INT32:s[0-9]+]], [[FLOAT32]]