[llvm] r244604 - fix minsize detection: minsize attribute implies optimizing for size

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 11 07:31:14 PDT 2015


Author: spatel
Date: Tue Aug 11 09:31:14 2015
New Revision: 244604

URL: http://llvm.org/viewvc/llvm-project?rev=244604&view=rev
Log:
fix minsize detection: minsize attribute implies optimizing for size

Modified:
    llvm/trunk/lib/CodeGen/MachineCombiner.cpp
    llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll

Modified: llvm/trunk/lib/CodeGen/MachineCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCombiner.cpp?rev=244604&r1=244603&r2=244604&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCombiner.cpp Tue Aug 11 09:31:14 2015
@@ -426,9 +426,7 @@ bool MachineCombiner::runOnMachineFuncti
   MRI = &MF.getRegInfo();
   Traces = &getAnalysis<MachineTraceMetrics>();
   MinInstr = 0;
-
-  // FIXME: Use Function::optForSize().
-  OptSize = MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
+  OptSize = MF.getFunction()->optForSize();
 
   DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
   if (!TII->useMachineCombiner()) {

Modified: llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll?rev=244604&r1=244603&r2=244604&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/mul-lohi.ll Tue Aug 11 09:31:14 2015
@@ -37,10 +37,11 @@ define i128 @test_128bitmul_optsize(i128
 
 define i128 @test_128bitmul_minsize(i128 %lhs, i128 %rhs) minsize {
 ; CHECK-LABEL: test_128bitmul_minsize:
-; CHECK-DAG: mul [[PART1:x[0-9]+]], x0, x3
-; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
-; CHECK: mul [[PART2:x[0-9]+]], x1, x2
-; CHECK: mul x0, x0, x2
+; CHECK:       umulh [[HI:x[0-9]+]], x0, x2
+; CHECK-NEXT:  madd  [[TEMP1:x[0-9]+]], x0, x3, [[HI]]
+; CHECK-NEXT:  madd  x1, x1, x2, [[TEMP1]]
+; CHECK-NEXT:  mul   x0, x0, x2
+; CHECK-NEXT:  ret
 
   %prod = mul i128 %lhs, %rhs
   ret i128 %prod




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