[PATCH] D11937: Teach Sparc assembler about %fprs

[Joerg Sonnenberger via llvm-commits]

joerg created this revision.
joerg added reviewers: llvm-commits, venkatra.

Add support for reading/writing the FPRS register.

http://reviews.llvm.org/D11937

Files:
  lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
  lib/Target/Sparc/SparcInstrInfo.td
  lib/Target/Sparc/SparcRegisterInfo.td
  test/MC/Sparc/sparcv9-instructions.s

Index: test/MC/Sparc/sparcv9-instructions.s
===================================================================
--- test/MC/Sparc/sparcv9-instructions.s
+++ test/MC/Sparc/sparcv9-instructions.s
@@ -52,3 +52,13 @@
         ! V8-NEXT: lduwa [%i0 + %l6] 131, %o2
         ! V9: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
         lduwa [%i0 + %l6] 131, %o2
+
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: rd %fprs, %i0
+        ! V9: rd %fprs, %i0          ! encoding: [0xb1,0x41,0x80,0x00]
+        rd %fprs, %i0
+
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: wr %i0, 7, %fprs
+        ! V9: wr %i0, 7, %fprs       ! encoding: [0x8d,0x86,0x20,0x07]
+        wr %i0, 7, %fprs
Index: lib/Target/Sparc/SparcRegisterInfo.td
===================================================================
--- lib/Target/Sparc/SparcRegisterInfo.td
+++ lib/Target/Sparc/SparcRegisterInfo.td
@@ -99,6 +99,8 @@
 def PSR : SparcCtrlReg<0, "PSR">;
 def WIM : SparcCtrlReg<0, "WIM">;
 def TBR : SparcCtrlReg<0, "TBR">;
+// FPRS is SparcV9 only.
+def FPRS : SparcCtrlReg<0, "FPRS">;
 
 // Integer registers
 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
Index: lib/Target/Sparc/SparcInstrInfo.td
===================================================================
--- lib/Target/Sparc/SparcInstrInfo.td
+++ lib/Target/Sparc/SparcInstrInfo.td
@@ -787,6 +787,18 @@
 		     "rd %tbr, $rd", []>;
 }
 
+let Predicates = [HasV9] in {
+  let rs2 = 0, rs1 = 6, Uses=[FPRS] in
+    def RDFPRS : F3_1<2, 0b101000,
+                     (outs IntRegs:$rd), (ins),
+                     "rd %fprs, $rd", []>;
+
+  let rd = 6, Defs=[FPRS] in
+    def WRFPRSri : F3_2<2, 0b110000,
+                     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
+                     "wr $rs1, $simm13, %fprs", []>;
+}
+
 // Section B.29 - Write State Register Instructions
 def WRASRrr : F3_1<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
Index: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
===================================================================
--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -778,6 +778,9 @@
       case Sparc::TBR:
         Op = SparcOperand::CreateToken("%tbr", S);
         break;
+      case Sparc::FPRS:
+        Op = SparcOperand::CreateToken("%fprs", S);
+        break;
       case Sparc::ICC:
         if (name == "xcc")
           Op = SparcOperand::CreateToken("%xcc", S);
@@ -902,6 +905,12 @@
       return true;
     }
 
+    if (name.equals("fprs")) {
+      RegNo = Sparc::FPRS;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+
     if (name.equals("xcc")) {
       // FIXME:: check 64bit.
       RegNo = Sparc::ICC;


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