[llvm] r244591 - [ARM] Replace ARMISD::VMINNM/VMAXNM with ISD::FMINNUM/FMAXNUM
James Molloy via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 05:06:22 PDT 2015
Author: jamesm
Date: Tue Aug 11 07:06:22 2015
New Revision: 244591
URL: http://llvm.org/viewvc/llvm-project?rev=244591&view=rev
Log:
[ARM] Replace ARMISD::VMINNM/VMAXNM with ISD::FMINNUM/FMAXNUM
NFCI. This replaces another custom ISDNode with a generic equivalent.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=244591&r1=244590&r2=244591&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Aug 11 07:06:22 2015
@@ -932,6 +932,8 @@ ARMTargetLowering::ARMTargetLowering(con
setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal);
+ setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
if (!Subtarget->isFPOnlySP()) {
setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
setOperationAction(ISD::FCEIL, MVT::f64, Legal);
@@ -939,6 +941,8 @@ ARMTargetLowering::ARMTargetLowering(con
setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
setOperationAction(ISD::FRINT, MVT::f64, Legal);
+ setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
}
}
@@ -1146,8 +1150,6 @@ const char *ARMTargetLowering::getTarget
case ARMISD::UMLAL: return "ARMISD::UMLAL";
case ARMISD::SMLAL: return "ARMISD::SMLAL";
case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
- case ARMISD::VMAXNM: return "ARMISD::VMAX";
- case ARMISD::VMINNM: return "ARMISD::VMIN";
case ARMISD::BFI: return "ARMISD::BFI";
case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
@@ -3661,26 +3663,26 @@ SDValue ARMTargetLowering::LowerSELECT_C
case ISD::SETOGE:
if (!DAG.isKnownNeverNaN(RHS))
break;
- return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
+ return DAG.getNode(ISD::FMAXNUM, dl, VT, LHS, RHS);
case ISD::SETUGT:
case ISD::SETUGE:
if (!DAG.isKnownNeverNaN(LHS))
break;
case ISD::SETGT:
case ISD::SETGE:
- return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
+ return DAG.getNode(ISD::FMAXNUM, dl, VT, LHS, RHS);
case ISD::SETOLT:
case ISD::SETOLE:
if (!DAG.isKnownNeverNaN(RHS))
break;
- return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
+ return DAG.getNode(ISD::FMINNUM, dl, VT, LHS, RHS);
case ISD::SETULT:
case ISD::SETULE:
if (!DAG.isKnownNeverNaN(LHS))
break;
case ISD::SETLT:
case ISD::SETLE:
- return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
+ return DAG.getNode(ISD::FMINNUM, dl, VT, LHS, RHS);
}
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=244591&r1=244590&r2=244591&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Aug 11 07:06:22 2015
@@ -173,10 +173,6 @@ namespace llvm {
// BUILD_VECTOR for this purpose.
BUILD_VECTOR,
- // Floating-point max and min:
- VMAXNM,
- VMINNM,
-
// Bit-field insert
BFI,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=244591&r1=244590&r2=244591&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 11 07:06:22 2015
@@ -71,9 +71,6 @@ def SDT_ARMTCRET : SDTypeProfile<0, 1, [
def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
-def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
-def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
-
def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
[SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>,
@@ -180,9 +177,6 @@ def ARMtcret : SDNode<"ARMISD::T
def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
-def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
-def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
-
//===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions.
//
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=244591&r1=244590&r2=244591&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Aug 11 07:06:22 2015
@@ -393,8 +393,8 @@ multiclass vmaxmin_inst<string op, bit o
}
}
-defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>;
-defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>;
+defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>;
+defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
// Match reassociated forms only if not sign dependent rounding.
def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
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