[llvm] r244529 - MIR Serialization: Serialize the liveout register mask machine operands.
Alex Lorenz via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 10 16:24:43 PDT 2015
Author: arphaman
Date: Mon Aug 10 18:24:42 2015
New Revision: 244529
URL: http://llvm.org/viewvc/llvm-project?rev=244529&view=rev
Log:
MIR Serialization: Serialize the liveout register mask machine operands.
Added:
llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir
Modified:
llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=244529&r1=244528&r2=244529&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp Mon Aug 10 18:24:42 2015
@@ -201,6 +201,7 @@ static MIToken::TokenKind getIdentifierK
.Case("non-temporal", MIToken::kw_non_temporal)
.Case("invariant", MIToken::kw_invariant)
.Case("align", MIToken::kw_align)
+ .Case("liveout", MIToken::kw_liveout)
.Default(MIToken::Identifier);
}
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=244529&r1=244528&r2=244529&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.h (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.h Mon Aug 10 18:24:42 2015
@@ -70,6 +70,7 @@ struct MIToken {
kw_non_temporal,
kw_invariant,
kw_align,
+ kw_liveout,
// Identifier tokens
Identifier,
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=244529&r1=244528&r2=244529&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Mon Aug 10 18:24:42 2015
@@ -121,6 +121,7 @@ public:
bool parseIRBlock(BasicBlock *&BB, const Function &F);
bool parseBlockAddressOperand(MachineOperand &Dest);
bool parseTargetIndexOperand(MachineOperand &Dest);
+ bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
bool parseMachineOperand(MachineOperand &Dest);
bool parseMachineOperandAndTargetFlags(MachineOperand &Dest);
bool parseOffset(int64_t &Offset);
@@ -920,6 +921,33 @@ bool MIParser::parseTargetIndexOperand(M
return false;
}
+bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
+ assert(Token.is(MIToken::kw_liveout));
+ const auto *TRI = MF.getSubtarget().getRegisterInfo();
+ assert(TRI && "Expected target register info");
+ uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
+ lex();
+ if (expectAndConsume(MIToken::lparen))
+ return true;
+ while (true) {
+ if (Token.isNot(MIToken::NamedRegister))
+ return error("expected a named register");
+ unsigned Reg = 0;
+ if (parseRegister(Reg))
+ return true;
+ lex();
+ Mask[Reg / 32] |= 1U << (Reg % 32);
+ // TODO: Report an error if the same register is used more than once.
+ if (Token.isNot(MIToken::comma))
+ break;
+ lex();
+ }
+ if (expectAndConsume(MIToken::rparen))
+ return true;
+ Dest = MachineOperand::CreateRegLiveOut(Mask);
+ return false;
+}
+
bool MIParser::parseMachineOperand(MachineOperand &Dest) {
switch (Token.kind()) {
case MIToken::kw_implicit:
@@ -970,6 +998,8 @@ bool MIParser::parseMachineOperand(Machi
return parseBlockAddressOperand(Dest);
case MIToken::kw_target_index:
return parseTargetIndexOperand(Dest);
+ case MIToken::kw_liveout:
+ return parseLiveoutRegisterMaskOperand(Dest);
case MIToken::Error:
return true;
case MIToken::Identifier:
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=244529&r1=244528&r2=244529&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Mon Aug 10 18:24:42 2015
@@ -645,6 +645,21 @@ void MIPrinter::print(const MachineOpera
llvm_unreachable("Can't print this machine register mask yet.");
break;
}
+ case MachineOperand::MO_RegisterLiveOut: {
+ const uint32_t *RegMask = Op.getRegLiveOut();
+ OS << "liveout(";
+ bool IsCommaNeeded = false;
+ for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
+ if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
+ if (IsCommaNeeded)
+ OS << ", ";
+ printReg(Reg, OS, TRI);
+ IsCommaNeeded = true;
+ }
+ }
+ OS << ")";
+ break;
+ }
case MachineOperand::MO_Metadata:
Op.getMetadata()->printAsOperand(OS, MST);
break;
Added: llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir?rev=244529&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/X86/liveout-register-mask.mir Mon Aug 10 18:24:42 2015
@@ -0,0 +1,43 @@
+# RUN: llc -march=x86-64 -start-after stackmap-liveness -stop-after stackmap-liveness -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses the liveout register mask
+# machine operands correctly.
+
+--- |
+
+ define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
+ entry:
+ %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
+ ret void
+ }
+
+ declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+
+...
+---
+name: small_patchpoint_codegen
+tracksRegLiveness: true
+liveins:
+ - { reg: '%rdi' }
+ - { reg: '%rsi' }
+frameInfo:
+ hasPatchPoint: true
+ stackSize: 8
+ adjustsStack: true
+ hasCalls: true
+fixedStack:
+ - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
+body:
+ - id: 0
+ name: entry
+ liveins: [ '%rdi', '%rsi', '%rbp' ]
+ instructions:
+ - 'frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'
+ - CFI_INSTRUCTION .cfi_def_cfa_offset 16
+ - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'
+ - '%rbp = frame-setup MOV64rr %rsp'
+ - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'
+# CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),
+ - 'PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax'
+ - '%rbp = POP64r implicit-def %rsp, implicit %rsp'
+ - RETQ
+...
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