[llvm] r244519 - Add support for the signx instrution alias of SPARCv9.

[Joerg Sonnenberger via llvm-commits]

Author: joerg
Date: Mon Aug 10 17:32:25 2015
New Revision: 244519

URL: http://llvm.org/viewvc/llvm-project?rev=244519&view=rev
Log:
Add support for the signx instrution alias of SPARCv9.

Modified:
    llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
    llvm/trunk/test/MC/Sparc/sparcv9-instructions.s

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td?rev=244519&r1=244518&r2=244519&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td Mon Aug 10 17:32:25 2015
@@ -450,3 +450,8 @@ def : InstAlias<"fcmpeq $rs1, $rs2", (V9
                                                      QFPRegs:$rs2)>,
                 Requires<[HasHardQuad]>;
 
+// signx rd -> sra rd, %g0, rd
+def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
+
+// signx reg, rd -> sra reg, %g0, rd
+def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;

Modified: llvm/trunk/test/MC/Sparc/sparcv9-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparcv9-instructions.s?rev=244519&r1=244518&r2=244519&view=diff
==============================================================================
--- llvm/trunk/test/MC/Sparc/sparcv9-instructions.s (original)
+++ llvm/trunk/test/MC/Sparc/sparcv9-instructions.s Mon Aug 10 17:32:25 2015
@@ -26,3 +26,12 @@
         ! V9:      popc %g1, %g2                ! encoding: [0x85,0x70,0x00,0x01]
         popc %g1, %g2
 
+
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: signx %g1, %g2
+        ! V9: sra %g1, %g0, %g2               ! encoding: [0x85,0x38,0x40,0x00]
+        signx %g1, %g2
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: signx %g1
+        ! V9: sra %g1, %g0, %g1               ! encoding: [0x83,0x38,0x40,0x00]
+        signx %g1