[PATCH] D11764: [DAGCombiner] Attempt to mask vectors before zero extension instead of after.

[Ulrich Weigand]

uweigand added a comment.

> Ulrich - this includes some test changes in SystemZ, please can you check them? A quick search inducates they make sense but I want to make sure.


Well, the changed assembly is still *correct*, but it is somewhat less efficient than what we had before.

The problem is that we do have special "zero-extend" instructions (llgcr/llghr) which should be preferred over a generic rotate-then-insert-selected-bits (risbg) when possible.  However, the instruction patterns for the zero-extend instructions attempt to match the SelectionDAG patterns the middle end used to generate for those scenarios.  If we change those, the back end really ought to adapted to match the new patterns as well.

Unfortunately I'm currently travelling; I'll be able to look into this in more detail when I'm back mid next week.


Repository:
  rL LLVM

http://reviews.llvm.org/D11764