[PATCH] MIR Serialization: Serialize the UsesPhysRegMask from machine register info.
Duncan P. N. Exon Smith
dexonsmith at apple.com
Wed Aug 5 14:17:23 PDT 2015
> On 2015-Jul-30, at 16:47, Alex L <arphaman at gmail.com> wrote:
>
> Hi,
>
> This patch serializes the UsesPhysRegMask register mask from the machine register
> information class. The mask is serialized as an inverted 'calleeSavedRegisters' mask
> to keep the output minimal. It uses the following syntax:
>
> calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
> '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
> '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
> '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
>
> As you can see, the sub registers are included in this mask as well.
>
> This patch also allows the MIR parser to infer this mask from the register mask
> operands if the machine function doesn't specify it.
>
> Cheers,
> Alex
> <0001-MIR-Serialization-serialize-the-UsesPhysRegMask-from.patch>
> From ca446d1f7a90691ffcc0c1ac16855e5b0eb7a9d0 Mon Sep 17 00:00:00 2001
> From: Alex Lorenz <arphaman at gmail.com>
> Date: Thu, 30 Jul 2015 16:37:25 -0700
> Subject: [PATCH] MIR Serialization: serialize the UsesPhysRegMask from
> register info
>
> ---
> include/llvm/CodeGen/MIRYamlMapping.h | 2 +
> include/llvm/CodeGen/MachineRegisterInfo.h | 4 +
> lib/CodeGen/MIRParser/MIRParser.cpp | 31 ++++++++
> lib/CodeGen/MIRPrinter.cpp | 12 +++
> .../MIR/X86/used-physical-register-info.mir | 89 ++++++++++++++++++++++
> 5 files changed, 138 insertions(+)
> create mode 100644 test/CodeGen/MIR/X86/used-physical-register-info.mir
>
> diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp
> index f34cef7..9ce7e19 100644
> --- a/lib/CodeGen/MIRPrinter.cpp
> +++ b/lib/CodeGen/MIRPrinter.cpp
> @@ -213,6 +213,18 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
> printReg(I->second, LiveIn.VirtualRegister, TRI);
> MF.LiveIns.push_back(LiveIn);
> }
> + // The used physical register mask is printed as an inverted callee saved
> + // register mask.
> + const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
> + if (UsedPhysRegMask.none())
> + return;
Will this cause a problem on the parsing side? In particular, won't the
reader infer "the default set" here? To put it another way, how do you
express in MIR that no registers should be marked callee-saved?
> + for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
> + if (!UsedPhysRegMask[I]) {
> + yaml::FlowStringValue Reg;
> + printReg(I, Reg, TRI);
> + MF.CalleeSavedRegisters.push_back(Reg);
> + }
> + }
> }
>
> void MIRPrinter::convert(ModuleSlotTracker &MST,
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