[llvm] r243984 - Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
Hans Wennborg
hans at chromium.org
Wed Aug 5 11:47:50 PDT 2015
On Tue, Aug 4, 2015 at 8:50 AM, Daniel Sanders
<Daniel.Sanders at imgtec.com> wrote:
> Thanks for looking into this. I remember reverting this commit in 3.6.2 and planning to fix it properly on trunk but the real fix has taken longer than expected. The first of the two parts to fix it is D10970.
>
> I'm ok with merging this revert to 3.7.0. I'll re-test with that revert applied as soon as I can.
I've merged this revert (r243984) in r244096.
Thanks,
Hans
> ________________________________________
> From: Vasileios Kalintiris
> Sent: 04 August 2015 15:50
> To: llvm-commits at cs.uiuc.edu
> Cc: hans at chromium.org; Daniel Sanders
> Subject: RE: [llvm] r243984 - Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
>
> Hi Hans,
>
> By reverting r229675 we fix the test-failures that Daniel mentioned in the other thread (tramp3d-v4 and kimwitu++/kc). The same commit was reverted in the 3.6.2 release (see http://llvm.org/viewvc/llvm-project?view=revision&revision=235869). Can we merge this to the branch too?
>
> Also, there's a patch under review that fixes the underlying issue and, once approved, it will allow us to re-apply this patch.
>
> Thanks,
> V. Kalintiris
>
> ________________________________________
> From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] on behalf of Vasileios Kalintiris
> Sent: 04 August 2015 15:26
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r243984 - Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
>
> Author: vkalintiris
> Date: Tue Aug 4 09:26:35 2015
> New Revision: 243984
>
> URL: http://llvm.org/viewvc/llvm-project?rev=243984&view=rev
> Log:
> Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.
>
> It introduced two regressions on 64-bit big-endian targets running under N32
> (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
> MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets
> comparisons such as BEQ compare the whole GPR64 but incorrectly tell the
> instruction selector that they operate on GPR32's. This leads to the
> elimination of i32->i64 extensions that are actually required by
> comparisons to work correctly.
>
> There's currently a patch under review that fixes this problem.
>
> Modified:
> llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
> llvm/trunk/test/CodeGen/Mips/delay-slot-kill.ll
> llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
> llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
> llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll
>
> Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=243984&r1=243983&r2=243984&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Aug 4 09:26:35 2015
> @@ -500,14 +500,6 @@ def : MipsPat<(trunc (assertzext GPR64:$
> def : MipsPat<(i32 (trunc GPR64:$src)),
> (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
>
> -// Bypass trunc nodes for bitwise ops.
> -def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
> - (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
> -def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
> - (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
> -def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
> - (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
> -
> // variable shift instructions patterns
> def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
> (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
>
> Modified: llvm/trunk/test/CodeGen/Mips/delay-slot-kill.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/delay-slot-kill.ll?rev=243984&r1=243983&r2=243984&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/delay-slot-kill.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/delay-slot-kill.ll Tue Aug 4 09:26:35 2015
> @@ -1,4 +1,6 @@
> ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
> +; We have to XFAIL this temporarily because of the reversion of r229675.
> +; XFAIL: *
>
> ; Currently, the following IR assembly generates a KILL instruction between
> ; the bitwise-and instruction and the return instruction. We verify that the
>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll?rev=243984&r1=243983&r2=243984&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll Tue Aug 4 09:26:35 2015
> @@ -59,7 +59,10 @@ define signext i32 @and_i32(i32 signext
> entry:
> ; ALL-LABEL: and_i32:
>
> - ; ALL: and $2, $4, $5
> + ; GP32: and $2, $4, $5
> +
> + ; GP64: and $[[T0:[0-9]+]], $4, $5
> + ; GP64: sll $2, $[[T0]], 0
>
> %r = and i32 %a, %b
> ret i32 %r
>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll?rev=243984&r1=243983&r2=243984&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll Tue Aug 4 09:26:35 2015
> @@ -59,7 +59,11 @@ define signext i32 @or_i32(i32 signext %
> entry:
> ; ALL-LABEL: or_i32:
>
> - ; ALL: or $2, $4, $5
> + ; GP32: or $2, $4, $5
> +
> + ; GP64: or $[[T0:[0-9]+]], $4, $5
> + ; FIXME: The sll instruction below is redundant.
> + ; GP64: sll $2, $[[T0]], 0
>
> %r = or i32 %a, %b
> ret i32 %r
>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll?rev=243984&r1=243983&r2=243984&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll Tue Aug 4 09:26:35 2015
> @@ -59,7 +59,10 @@ define signext i32 @xor_i32(i32 signext
> entry:
> ; ALL-LABEL: xor_i32:
>
> - ; ALL: xor $2, $4, $5
> + ; GP32: xor $2, $4, $5
> +
> + ; GP64: xor $[[T0:[0-9]+]], $4, $5
> + ; GP64: sll $2, $[[T0]], 0
>
> %r = xor i32 %a, %b
> ret i32 %r
>
>
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