[llvm] [PATCH 2/2] AMDGPU: Add MEM_RAT WRITE_TYPED.

[Zoltán Gilián]

> Does this need hasSideEffects = 1 set on it if it has the EOP bit?

I don't know what are the implications of setting that flag. The
MEM_RAT_CACHELESS instructions don't have it set though.

On Tue, Aug 4, 2015 at 12:18 AM, Matt Arsenault
<Matthew.Arsenault at amd.com> wrote:
> On 08/03/2015 04:02 AM, Zoltan Gilian wrote:
>
> ---
>  include/llvm/IR/IntrinsicsAMDGPU.td        |  5 +++++
>  lib/Target/AMDGPU/EvergreenInstructions.td | 10 ++++++++++
>  lib/Target/AMDGPU/R600ISelLowering.cpp     |  8 ++++++++
>  3 files changed, 23 insertions(+)
>
>
> Needs a test
>
>
>
> diff --git a/include/llvm/IR/IntrinsicsAMDGPU.td
> b/include/llvm/IR/IntrinsicsAMDGPU.td
> index 510e5ad..d7d0e3c 100644
> --- a/include/llvm/IR/IntrinsicsAMDGPU.td
> +++ b/include/llvm/IR/IntrinsicsAMDGPU.td
> @@ -33,6 +33,11 @@ defm int_r600_read_tgid :
> R600ReadPreloadRegisterIntrinsic_xyz <
>                                         "__builtin_r600_read_tgid">;
>  defm int_r600_read_tidig : R600ReadPreloadRegisterIntrinsic_xyz <
>                                         "__builtin_r600_read_tidig">;
> +
> +def int_r600_rat_write_typed :
> +  Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], []>,
> +  GCCBuiltin<"__builtin_r600_rat_write_typed">;
> +
>  } // End TargetPrefix = "r600"
>
>  let TargetPrefix = "AMDGPU" in {
> diff --git a/lib/Target/AMDGPU/EvergreenInstructions.td
> b/lib/Target/AMDGPU/EvergreenInstructions.td
> index 7adcd46..6e46748 100644
> --- a/lib/Target/AMDGPU/EvergreenInstructions.td
> +++ b/lib/Target/AMDGPU/EvergreenInstructions.td
> @@ -105,8 +105,18 @@ def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS
> <0x2, 0, 0xf,
>    [(global_store v4i32:$rw_gpr, i32:$index_gpr)]
>  >;
>
> +def RAT_WRITE_TYPED_eg : CF_MEM_RAT <0x1, ?,
> +  (ins R600_Reg128:$rw_gpr, R600_Reg128:$index_gpr, i32imm:$rat_id,
> InstFlag:$eop),
> +  "STORE_TYPED RAT($rat_id) $rw_gpr, $index_gpr, $eop",
> +  []
> +>;
>
> Does this need hasSideEffects = 1 set on it if it has the EOP bit?
>
> +
>  } // End usesCustomInserter = 1
>
> +def : Pat<(int_r600_rat_write_typed R600_Reg128:$rw_gpr,
> R600_Reg128:$index_gpr, (i32 imm:$rat_id)),
> +    (RAT_WRITE_TYPED_eg $rw_gpr, $index_gpr, imm:$rat_id)
> +  >;
> +
>
>
> I think you should be able to put this pattern directly in the instruction
> definition, unless this is one of those instructions that changes encoding
> on Cayman etc. In that case this should be a multiclass and instantiated
> with each subtarget.
>
>  class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag>
> pattern>
>      : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
>
> diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp
> b/lib/Target/AMDGPU/R600ISelLowering.cpp
> index be6f65d..f825b90 100644
> --- a/lib/Target/AMDGPU/R600ISelLowering.cpp
> +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
> @@ -287,6 +287,14 @@ MachineBasicBlock *
> R600TargetLowering::EmitInstrWithCustomInserter(
>              .addImm(IsEOP(I)); // Set End of program bit
>      break;
>    }
> +  case AMDGPU::RAT_WRITE_TYPED_eg: {
> +    BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
> +            .addOperand(MI->getOperand(0))
> +            .addOperand(MI->getOperand(1))
> +            .addOperand(MI->getOperand(2))
> +            .addImm(IsEOP(I)); // Set End of program bit
> +    break;
> +  }
>
>    case AMDGPU::TXD: {
>      unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
> --
> 2.4.6
>
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