[PATCH] D11702: AMDGPU: Make scc not allocatable

[Matt Arsenault]

arsenm created this revision.
arsenm added a reviewer: tstellarAMD.
arsenm added a subscriber: llvm-commits.

This fixes an assertion in the SIInsertWait pass when i32 is removed from scc.

http://reviews.llvm.org/D11702

Files:
  lib/Target/AMDGPU/SIRegisterInfo.td

Index: lib/Target/AMDGPU/SIRegisterInfo.td
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.td
+++ lib/Target/AMDGPU/SIRegisterInfo.td
@@ -184,6 +184,7 @@
 
 // Special register classes for predicates and the M0 register
 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
+  let isAllocatable = 0;
   let CopyCost = -1; // Theoretically it is possible to read from SCC,
                      // but it should never be necessary.
 }


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