[RFC] SortedVector ADT

[Krzysztof Parzyszek]

On 7/31/2015 11:02 AM, Puyan Lotfi wrote:
>
> Originally I had added a patch to improve compile time in
> VirtRegRewriter, and me and Quentin had noticed that these LiveIns set
> in MachineBasicBlock
> we not actually in sorted order in all cases. We thought this could be a
> good way to maintain the ordering for the LiveIns set with low overhead
> since they were mostly sorted as a result of how they were being
> inserted into.

Can we use BitVector for physical vectors?  They are pretty much 
constant in terms of read/write time.  The only concern would be memory 
consumption, but even then only AMDGPU seems to have a considerable 
number of registers.  Maybe some combination that uses BitVector for 
small numbers and something else otherwise would do the trick?

AArch64GenRegisterInfo.inc:  NUM_TARGET_REGS       // 484
AMDGPUGenRegisterInfo.inc:  NUM_TARGET_REGS  // 3418
ARMGenRegisterInfo.inc:  NUM_TARGET_REGS        // 289
BPFGenRegisterInfo.inc:  NUM_TARGET_REGS        // 13
HexagonGenRegisterInfo.inc:  NUM_TARGET_REGS       // 78
MipsGenRegisterInfo.inc:  NUM_TARGET_REGS      // 418
MSP430GenRegisterInfo.inc:  NUM_TARGET_REGS  // 33
NVPTXGenRegisterInfo.inc:  NUM_TARGET_REGS    // 86
PPCGenRegisterInfo.inc:  NUM_TARGET_REGS    // 310
SparcGenRegisterInfo.inc:  NUM_TARGET_REGS    // 153
SystemZGenRegisterInfo.inc:  NUM_TARGET_REGS       // 162
X86GenRegisterInfo.inc:  NUM_TARGET_REGS        // 246
XCoreGenRegisterInfo.inc:  NUM_TARGET_REGS    // 17

-Krzysztof


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