[PATCH] D11604: AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on SI

[Tom Stellard]

tstellarAMD added inline comments.

================
Comment at: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1587-1589
@@ +1586,5 @@
+bool AMDGPUOperand::isSMRDLiteralOffset() const {
+  // 32-bit literals are only supported on CI and we only want to use them
+  // when the offset is > 8-bits.
+  return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
+}
----------------
arsenm wrote:
> tstellarAMD wrote:
> > Are you concerned that the value 0xff will be read as SRC_LITERAL rather than the actual offset?  Because there is no way to specify SRC_LITERAL using the assembler.
> Yes. My understanding was you can't use 255 because that is the same as SRC_LITERAL and both are set in the same immediate field. The meaning of 255 would then change meaning depending on SI/CI.
The meaning of 255 is controled by the IMM bit, so there shouldn't be an issue.
The encoding looks like this:

8-bit offset (0xff)
offset = 0xff
imm = 1

32-bit offset
offset = 0xff
imm = 0


http://reviews.llvm.org/D11604