[PATCH] D11471: Scalar to vector conversions using direct moves

Bill Schmidt wschmidt at linux.vnet.ibm.com
Wed Jul 29 13:10:36 PDT 2015


wschmidt added inline comments.

================
Comment at: test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll:74
@@ +73,3 @@
+; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1
+; CHECK-LE: xxsldwi {{[0-9]+}}, [[REG1]], [[REG1]], 1
+}
----------------
nemanjai wrote:
> wschmidt wrote:
> > I was confused by this at first, but now I get it.  In all of these tests, the code generation that you are checking for is just for the %splat.splatinsert calculation, right?  This is the part that translates into a scalar_to_vector node.  I assume that the generated code follows this up with code to splat element 0 to the entire result register, correct?
> Yes, the subsequent instruction will be a splat (VSX if we have one, VMX otherwise). I can add those to the check patterns but, I can't verify the correct register (because of the "off-by-32 relationship" between the VSX and VMX registers). I was actually hoping to use the FileCheck capability of checking line numbers (ranges), but that actually looks for the word line I think. So I can add the CHECK: vsplat[bhw] and just confirm the right element in the splat instruction if you'd like.
No, that's ok.  Just add a comment at the beginning of the file indicating that you are just checking the code generated for the insertelement.  Alternatively, you can make this more obvious by putting the CHECK comment lines right after the insertelement in each test variant.


Repository:
  rL LLVM

http://reviews.llvm.org/D11471







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