[PATCH] D11327: [X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit.

[Simon Pilgrim]

RKSimon added a comment.

In http://reviews.llvm.org/D11327#214333, @qcolombet wrote:

> Thanks for the updated version. I have mixed feeling about it though. Indeed, I think the code is correct, but given how the lowering works, I believe we cannot reach it.
>  In other words, currently, I do not think we can produce a test case that covers this code. If you can add a test case to cover it, then awesome :).
>
> How about not doing the transformation when the splat index is not covered by the first operand, so that if it happens we would have a test case to add with the code support it?


Yes the canonicalization in DAG.getVectorShuffle /should/ stop it happening. Would adding an assert to check the splat comes from the first operand be too harsh?


Repository:
  rL LLVM

http://reviews.llvm.org/D11327