[PATCH] D11471: Scalar to vector conversions using direct moves

[hfinkel at anl.gov]

hfinkel added inline comments.

================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7504
@@ +7503,3 @@
+  if (Subtarget.hasDirectMove()) {
+    SDValue Move = DAG.getNode(PPCISD::MTVSRDVEC, dl, Op.getValueType(),
+                               Op.getOperand(0));
----------------
Just return the result of the DAG.getNode(...) call. Then you don't even need the { } around the body of the if.

That having been said, it does not seem like you have to do this at all. Just declare the relevant SCALAR_TO_VECTOR as Legal, and pattern match it in the usual way in the .td file.

================
Comment at: lib/Target/PowerPC/PPCISelLowering.h:135
@@ +134,3 @@
+      /// Conversions between SP 64-bit values and SP 32-bit values
+      SP_TO_VEC_SP,
+      VEC_SP_TO_SP,
----------------
Why are you adding these? What generates them?

================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1198
@@ +1197,3 @@
+
+  // Conversions between vector and scalar single precision
+  def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
----------------
Given that I don't see anything that actually generates this ISD nodes, I'm suspicions that you don't actually have tests for these.

================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1236
@@ +1235,3 @@
+def Moves {
+  dag BE_BYTE = (MTVSRD
+                  (RLDICR
----------------
Maybe we should name this BE_LOW_BYTE, or something like that?



Repository:
  rL LLVM

http://reviews.llvm.org/D11471