[PATCH] D11463: [AArch64] Define subtarget feature "reserve-x18"
Eric Christopher
echristo at gmail.com
Thu Jul 23 13:50:18 PDT 2015
So you're defining it to true here and only have an option to set it to
true from the front end.
How would you turn it off? :)
-eric
On Thu, Jul 23, 2015 at 8:16 AM Akira Hatanaka <ahatanak at gmail.com> wrote:
> ahatanak created this revision.
> ahatanak added reviewers: echristo, dexonsmith.
> ahatanak added a subscriber: llvm-commits.
> Herald added subscribers: rengolin, aemerson.
>
> This patch defines a subtarget feature "reserve-x18" and uses it to decide
> whether X18 should be reserved.
>
> The clang-side patch which makes changes to pass a subtarget feature
> instead of a backend option is here: http://reviews.llvm.org/D11462
>
> http://reviews.llvm.org/D11463
>
> Files:
> lib/Target/AArch64/AArch64.td
> lib/Target/AArch64/AArch64RegisterInfo.cpp
> lib/Target/AArch64/AArch64Subtarget.h
> test/CodeGen/AArch64/arm64-platform-reg.ll
>
> Index: test/CodeGen/AArch64/arm64-platform-reg.ll
> ===================================================================
> --- test/CodeGen/AArch64/arm64-platform-reg.ll
> +++ test/CodeGen/AArch64/arm64-platform-reg.ll
> @@ -1,5 +1,5 @@
> ; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s
> --check-prefix=CHECK-RESERVE-X18
> -; RUN: llc -mtriple=arm64-freebsd-gnu -aarch64-reserve-x18 -o - %s |
> FileCheck %s --check-prefix=CHECK-RESERVE-X18
> +; RUN: llc -mtriple=arm64-freebsd-gnu -mattr=+reserve-x18 -o - %s |
> FileCheck %s --check-prefix=CHECK-RESERVE-X18
> ; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
>
> ; x18 is reserved as a platform register on Darwin but not on other
> Index: lib/Target/AArch64/AArch64Subtarget.h
> ===================================================================
> --- lib/Target/AArch64/AArch64Subtarget.h
> +++ lib/Target/AArch64/AArch64Subtarget.h
> @@ -51,6 +51,9 @@
> // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
> bool HasZeroCycleZeroing;
>
> + // ReserveX18 - X18 is not available as a general purpose register.
> + bool ReserveX18;
> +
> bool IsLittle;
>
> /// CPUString - String name of used CPU.
> @@ -101,6 +104,7 @@
>
> bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
>
> + bool isX18Reserved() const { return ReserveX18; }
> bool hasFPARMv8() const { return HasFPARMv8; }
> bool hasNEON() const { return HasNEON; }
> bool hasCrypto() const { return HasCrypto; }
> Index: lib/Target/AArch64/AArch64RegisterInfo.cpp
> ===================================================================
> --- lib/Target/AArch64/AArch64RegisterInfo.cpp
> +++ lib/Target/AArch64/AArch64RegisterInfo.cpp
> @@ -34,10 +34,6 @@
> #define GET_REGINFO_TARGET_DESC
> #include "AArch64GenRegisterInfo.inc"
>
> -static cl::opt<bool>
> -ReserveX18("aarch64-reserve-x18", cl::Hidden,
> - cl::desc("Reserve X18, making it unavailable as GPR"));
> -
> AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
> : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
>
> @@ -104,7 +100,7 @@
> Reserved.set(AArch64::W29);
> }
>
> - if (TT.isOSDarwin() || ReserveX18) {
> + if (TT.isOSDarwin() ||
> MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {
> Reserved.set(AArch64::X18); // Platform register
> Reserved.set(AArch64::W18);
> }
> @@ -131,7 +127,8 @@
> return true;
> case AArch64::X18:
> case AArch64::W18:
> - return TT.isOSDarwin() || ReserveX18;
> + return TT.isOSDarwin() ||
> + MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
> case AArch64::FP:
> case AArch64::W29:
> return TFI->hasFP(MF) || TT.isOSDarwin();
> @@ -402,9 +399,11 @@
> case AArch64::GPR32commonRegClassID:
> case AArch64::GPR64commonRegClassID:
> return 32 - 1 // XZR/SP
> - - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
> - - (TT.isOSDarwin() || ReserveX18) // X18 reserved as platform
> register
> - - hasBasePointer(MF); // X19
> + - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
> + - (TT.isOSDarwin() ||
> + MF.getSubtarget<AArch64Subtarget>()
> + .isX18Reserved()) // X18 reserved as platform register
> + - hasBasePointer(MF); // X19
> case AArch64::FPR8RegClassID:
> case AArch64::FPR16RegClassID:
> case AArch64::FPR32RegClassID:
> Index: lib/Target/AArch64/AArch64.td
> ===================================================================
> --- lib/Target/AArch64/AArch64.td
> +++ lib/Target/AArch64/AArch64.td
> @@ -40,6 +40,10 @@
> def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing",
> "true",
> "Has zero-cycle zeroing
> instructions">;
>
> +def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18",
> "true",
> + "Reserve X18, making it
> unavailable "
> + "as a GPR">;
> +
>
> //===----------------------------------------------------------------------===//
> // Architectures.
> //
>
>
>
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