[llvm] r243033 - This patch eanble register coalescing to coalesce the following:

[Weiming Zhao]

Author: weimingz
Date: Thu Jul 23 14:24:53 2015
New Revision: 243033

URL: http://llvm.org/viewvc/llvm-project?rev=243033&view=rev
Log:
This patch eanble register coalescing to coalesce the following:

  %vreg2<def> = MOVi32imm 1; GPR32:%vreg2
  %W1<def> = COPY %vreg2; GPR32:%vreg2
into:
  %W1<def> = MOVi32imm 1
Patched by Lawrence Hu (lawrence at codeaurora.org)


Added:
    llvm/trunk/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=243033&r1=243032&r2=243033&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Thu Jul 23 14:24:53 2015
@@ -533,6 +533,14 @@ void AArch64InstrInfo::insertSelect(Mach
       CC);
 }
 
+/// Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.
+static bool canBeExpandedToORR(const MachineInstr *MI, unsigned BitSize) {
+  uint64_t Imm = MI->getOperand(1).getImm();
+  uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
+  uint64_t Encoding;
+  return AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding);
+}
+
 // FIXME: this implementation should be micro-architecture dependent, so a
 // micro-architecture target hook should be introduced here in future.
 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
@@ -573,6 +581,12 @@ bool AArch64InstrInfo::isAsCheapAsAMove(
   case AArch64::ORRWrr:
   case AArch64::ORRXrr:
     return true;
+  // If MOVi32imm or MOVi64imm can be expanded into ORRWri or
+  // ORRXri, it is as cheap as MOV
+  case AArch64::MOVi32imm:
+    return canBeExpandedToORR(MI, 32);
+  case AArch64::MOVi64imm:
+    return canBeExpandedToORR(MI, 64);
   }
 
   llvm_unreachable("Unknown opcode to check as cheap as a move!");

Added: llvm/trunk/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll?rev=243033&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll Thu Jul 23 14:24:53 2015
@@ -0,0 +1,18 @@
+; RUN: llc < %s | FileCheck %s
+
+; CHECK:        orr     w0, wzr, #0x1
+; CHECK-NEXT :  bl      foo
+; CHECK-NEXT :  orr     w0, wzr, #0x1
+; CHECK-NEXT :  bl      foo
+
+target triple = "aarch64--linux-android"
+declare i32 @foo(i32)
+
+; Function Attrs: nounwind uwtable
+define i32 @main() {
+entry:
+  %call = tail call i32 @foo(i32 1)
+  %call1 = tail call i32 @foo(i32 1)
+  ret i32 0
+}
+